Catching Clock Integrity and Jitter Issues Before They Break Your Design

Two recent blog posts discussed the challenges of clock signal integrity and clock jitter in deep submicron semiconductor devices. Many factors degrade clock signals that start off as clean waveforms, and clock jitter produces unwanted timing variations. A dedicated clock analysis tool is requited to address these issues. The first post outlined the essential requirements for such a tool, and the second post discussed an available commercial solution. It also presented some real-world results from Arm and Socionext.

This post provides details from the Arm presentation “Mastering Uncertainty: Transforming High-Frequency Clock Planning and SignOff to Maximize PPA” at the SNUG Silicon Valley 2025 event. ARM began by describing their motivations for a solution to overcome uncertainty in clock signals. Clean clocks enable the best possible operating frequency (Fmax) and help to balance power versus performance trade-offs. This results in a better chip, but the benefits do not end at the design stage. Well-behaved clocks also enhance manufacturing yield, for more successful and reliable end products.

The Arm presenter listed their key requirements for a clock analysis tool:

• Accurate modelling of silicon conditions
• Clock integrity: Rail-to-rail swing and duty cycle distortion
• Clock integrity: Fresh and aging with targeted mission profiles
• Clock jitter: Period and cycle-to-cycle jitter due to power supply noise
• 100% coverage of all clock levels/points
• SPICE-level accuracy
• Efficient analysis of large volumes of data
• Optimized computing resources

Failure to condition clock signals properly produces multiple types of failures. Duty cycle distortion (DCD) occurs when there is imbalance in high and low clock pulse widths. This leads to timing violations and has an impact on metastability in flip-flops. Rail-to-rail (R2R) failures are due to insufficient voltage swing in the clock signals, producing incorrect state retention. Aging and IR drop effects are factors for this type of failure. Dead clock pulses are missing clock transitions, often due to excessive clock gating or power management. These can cause data synchronization issues, leading to system-level errors and unexpected halts. 

Modern chips are subject to clock integrity and jitter issues due to increased process variability, high frequences, and transistor mismatch. Unoptimized clock cells, low clock tree quality, poor clock routing, and noise in the power distribution network (PDN) make problems more likely. Effective and efficient clock analysis, including modeling the effects of aging on transistors and metal interconnect, enables the design of clock networks that will minimize issues throughout the silicon lifecycle.

For the 100M transistor chip design described in their talk, the Arm team selected Synopsys PrimeClock to meet their requirements and address their challenges. This solution provides scalable clock integrity and jitter analysis of both “fresh” and aging chips with SPICE-level accuracy. It enables full clock network analysis of individual clock domains and detailed analysis of point-to-point paths. It handles all types of configurations at all frequencies, including point-to-point clocks such as debug and mesh/H-tree based high frequency clocks.

PrimeClock accepts as inputs:

• Clock connectivity and implementation
• Synopsys PrimeTime results on worst corners with initial database
• Clock signoff specifications: R2R limits, DCD criteria, etc.
• Power supply noise

The clock analysis includes dynamic circuit checks with 100% coverage of the clock network and a focused jitter component. It reports weak nodes in the design, potential constraint issues with clocks, and the impact of aging on the clock network. The analysis is performed from the phase locked loop (PLL) or other clock source to all clock network leaf points. The DCD analysis is run at the worst corners to show how the duty cycle is distorted. In addition, the analysis checks to ensure that that there are no RTR failures within the signoff criteria for VDD and VSS. The plot and report below show the results for analysis of fresh (un-aged) silicon.

Clock jitter optimization is critical for timing closure and minimizing clock uncertainty. This helps the chip designers to improve Fmax and optimize power, performance, and area (PPA). PrimeClock checks for both period and cycle-to-cycle jitter, with the results shown in the outputs below. For period jitter, the left plot captures the maximum high pulse stretch across multiple cycles for each level and the right plot captures the minimum low pulse shrink across multiple cycles for each level, both with respect to the reference clock.

For cycle -to-cycle (C2C) jitter, the left plot captures the maximum high pulse stretch across multiple cycles for each level and the right plot captures the minimum low pulse shrink across multiple cycles for each level, both across adjacent cycles.

In terms of performance, the Arm team found that PrimeTime could analyze 100M transistors in reasonable time with SPICE accuracy using distributed mode. Specifically, they reported in their talk that the fresh analysis ran in 2 hours, the aging analysis in 4 hours, and the jitter analysis in 1.5 hours. 

The project results included:

• Clock integrity and jitter analysis successful deployed
• Analyzed complete clock structure from the PLL output to all endpoints
• Achieved acceptable runtime, meeting tape-out requirements
• Identified weak nodes on the clock structure with aging stress
• Analyzed RTR, DCD (fresh and aging with DC and AC stress), jitter, and SDC issues
• Used SPICE simulation to model transistor and interconnect non-linearities of clock paths
• Analyzed a huge design with 100M transistors using distributed mode in ~2 hours

The Arm presentation closed with a fitting one-line summary: "Clock integrity and jitter signoff achieved."