The Design Challenges of Clock Integrity and Clock Jitter

Signal integrity is one of the many challenges faced by chip designers. Deep submicron technologies are unfriendly hosts for the nice, clean signals desired. The culprits that compromise signal integrity and introduce jitter include thermal effects, manufacturing flaws, signal crosstalk, IR (voltage) drop, signal loss over long runs, reflections, electromagnetic interference (EMI), ground bounce, and noise in the power delivery network (PDN). Even when “fresh” chips have few issues, silicon aging effects degrade signals over the chip’s lifecycle.

The situation is bad enough for data signals, but even worse for clocks. Clocking networks run to every corner of the chip and control when storage elements trigger. Races, missed next-state values due to long paths, and metastability can result from corrupted clock signals. This post describes the challenges of clock network and clock jitter analysis in more detail and suggests a novel approach that has been shown in provide significant relief. Designers can increase their maximum operating clock frequency (Fmax) and make better power/performance tradeoffs.

There are two key failure mechanisms for clock signal integrity: rail to rail failures and duty-cycle distortion. Rail to rail failures occur when insufficient voltage swings in clock signals lead to incorrect state retention. Failure can happen at VDD, VSS, or both. Problems are more likely to arise as chips age. Duty-cycle distortion occurs when there are imbalances in high and low clock pulse widths. These can cause timing violations and lead to metastability in flip-flops.

Timing variation due to clock jitter is significant at high frequency/low voltage. Underestimating jitter can lead to timing failures. Overly pessimistic clock jitter results in over-margining and lower design performance. There are also two main types of clock jitter issues. Period jitter occurs when the clock frequency does not meet its designed value. A faster period can produce long path failures, while a longer period degrades chip performance. Whatever the average period, clocks may also suffer from cycle-to-cycle jitter because each cycle may vary longer or shorter than the previous cycle. This type of failure may also compromise performance or cause long paths, although in a seemingly random way that can be hard to debug.

Clock signals are particularly vulnerable to aging effects, making it hard to maintain integrity and minimize jitter in the field. Transistor aging may shift the threshold voltage, impacting delay and duty cycle stability. Long-term silicon degradation leads to failure over time. As metal interconnect ages, electromigration increases the resistance in clock routing, exacerbating IR effects. Further, capacitive and resistive degradation reduces the drive strength of clock buffers, causing increased jitter and skew in the clock distribution network.

Current basic simulation solutions are very inefficient and time consuming. They run for multiple days/weeks and cannot cover the full design clock network. Designers are looking for a spice-accurate solution that is scalable and an order of magnitude faster. A new approach is needed: a dedicated solution for clock integrity and jitter analysis to flag issues related to clock signals and optimize clock jitter settings for STA. Requirements for such a solution include:

• Highly optimized runtime to deliver results in hours, not days
• Tight integration with circuit simulation for SPICE-level accuracy
• Tight integration with STA for efficient timing flows and setup
• Application-specific techniques such as RC reduction and circuit pruning
• Support for all types of clock networks including clock mesh, clock trees, clock spines, etc.
• Highly scalable partitioning and distributed simulations

This analysis must be flexible enough to run at the block, subsystem, and full-chip level. Although some types of clock issues aren’t apparent until the entire network is analyzed, many problems can be detected much earlier at lower levels of the design hierarchy. This saves debug efforts and reduces time to market (TTM). Analysis can be run on block and subsystems after clock tree synthesis and routing, or on any level at the engineering changes order (ECO) and signoff stage. Designers can update their constraints to define more precise design margins and make surgical fixes as needed to eliminate errors.

Clock integrity analysis for both duty-cycle distortion and rail-to-rail swing should be performed for all clock pins in the clock network. There must be an option to add aging stress conditions and repeat the analysis if the fresh results are clean. Duty cycle distortion analysis is performed for both the fresh and clean cases.

Clock jitter analysis must check for both period and cycle-to-cycle jitter. Since jitter analysis based on transient simulation is runtime prohibitive, the solution must build a jitter model using a limited number of simulations and compute jitter by evaluating this model. Both clock integrity and jitter analysis must be capable of running on a complete clock domain, from the clock source to all the leaf points in the clock network, or through multiple clock domains automatically when both a “from” pin and a “to” pin are specified.

Dedicated clock integrity and jitter analysis has the potential to:

• Perform SPICE-accurate clock analysis that is scalable and an order of magnitude faster
• Identify structural clock issues quickly so that that they can be fixed easily
• Reduce pessimistic clock jitter margins and optimize for higher Fmax
• Run an order of magnitude faster with fewer compute resources than traditional flows
• Scale to handle designs with billions of transistors

This novel solution will be essential for high frequency designs, above 1GHz for lower voltage chips or above 2GHz for any voltage, and for advanced process nodes. It will apply to most leading-edge applications, including processors, high-performance computing (HPC), AI, and advanced automotive features. All designers of large, complex chips will want this at their fingertips.