HOME    TOOLS    VERIFICATION    FUNCTIONAL VERIFICATION

White Paper Download

Verifying Cache Coherency Protocols with Verification IP

The use of on-chip cache memory helps design teams optimize multicore designs for both power and performance. While the use of hardware to implement cache coherency enables design teams to improve SoC performance, it adds significantly to verification complexity. The use of verification IP (VIP) enables engineers to validate such designs, although the VIP's effectiveness depends on its advanced features and the extent of its support for the AMBA ACE protocol. Learn how a Reference Verification Platform (RVP) built with Synopsys' next-generation Discovery™ Verification IP (VIP) for the ARM® AMBA® 4 ACE™ protocol can be used to accelerate the verification of multicore SoCs.

To download this white paper, please complete the form below and click the "continue >>" button.

Required Required Fields

Business Email:Required
First Name:Required
Last Name:Required
Phone:Required
Job Role:Required
Job Title:Required
Company:Required
Division:Optional
Country:Required
Address 1:Required
Address 2:Optional
City:Required
State/Province:
Optional
Postal/Zip Code:Required


(requires browser cookies to be enabled)