Low DPPM Testing for Advanced Process Nodes and FinFETs
Most design teams rely on both stuck-at and transition delay tests from automatic test pattern generation (ATPG) to meet their manufacturing test quality goals at established process nodes. At advanced nodes, process variations give rise to physical defects that require additional tests for achieving low defective parts per million (DPPM). This paper highlights low DPPM test strategies and discusses how different physical defects associated with small-geometry processes impact the delay and leakage behavior of FinFET logic gates. We then show how leading-edge capabilities in Synopsys' TetraMAX® ATPG, such as slack-based transition delay testing and cell-aware testing, can be used to enable low DPPM testing for advanced process nodes and FinFETs.
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