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System-Level Benchmarking of AI workloads for TDA5 Performance Analysis and Optimization
As AI-driven automotive SoCs grow in complexity, engineering teams need accurate performance insight long before RTL and silicon are available. TI presents how Synopsys Platform Architect enables cycle-accurate AI workload analysis, helping teams identify bottlenecks, optimize hardware and software interactions, and make confident architecture decisions earlier in the TDA5 development cycle.
What You Will Learn
- How TI performs pre-RTL AI performance analysis using cycle-accurate models to evaluate NPU workloads, system behavior, and architectural tradeoffs before implementation begins.
- How Platform Architect enables system-level bottleneck identification by modeling memory subsystems, interconnects, memory controller contention, and layer-level AI inference performance within the context of the complete SoC.
- How early hardware-software co-optimization improves development outcomes by increasing confidence in performance projections, reducing reliance on late-stage emulation, lowering architecture rework risk, and accelerating design decisions.
Watch On-Demand
Featured Speakers
Asha Bhandarkar
TI
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