Scaling Expertise with AI Agents Across the Formal Workflow

Featured Speakers:

• Ghaith Bany Hamid, Senior Formal Verification Engineer, NVIDIA

Why You Should Watch This Session:

Recent advances in AI are transforming formal verification (FV) workflows in hardware design.

Domain-adapted large language models (LLMs) and generative AI, such as GenFV, automate complex tasks like assertion and helper property generation, addressing common challenges for Synopsys VC Formal users—including testbench development and overcoming the expertise barrier.

Traditionally, creating SystemVerilog Assertions, bind files, and auxiliary logic required significant manual effort and deep expertise. By integrating GenFV with EDA tools, users can benefit from automated property generation, iterative refinement, and democratized formal verification.

This session discusses how automated agentic systems further enhance productivity, accuracy, and coverage, while reducing the need for expert oversight. Although some challenges remain, GenFV marks a major step forward in making formal verification more efficient, scalable, and accessible for design engineers.