EDA
System
IP
SolvNetPlus
Training & Education
Reducing Risk in Chiplet Design: From IP Integration to First Silicon Success
Featured Speaker:
- Robert Kruger, Product Management Director, Synopsys
Presented at EE Times' The Road to Chiplet Scalability 2026, this session examines how IP, subsystem, and chiplet engagement models help accelerate development and improve first-silicon success. Using examples from AI accelerators, custom HBM architectures, and emerging physical AI applications, the presentation highlights strategies for reducing integration complexity and shifting validation earlier in the design cycle.
What You'll Learn:
- How system-level building blocks accelerate chiplet adoption
- Approaches for reducing integration and verification risk
- Best practices for improving first-silicon success
- Emerging trends in co-packaged optics and advanced 3D multi-die designs
Watch On-Demand
Featured Speaker
Robert Kruger
Product Management Director, Synopsys
Robert Kruger is a Product Management Director at Synopsys, where he oversees IP solutions for multi-die designs, including 2D, 3D, and 3.5D topologies. Throughout his career, Robert has held key roles in product marketing, business development, and roadmap planning at leading companies such as Intel, Broadcom, Nokia, and Altera. He brings extensive expertise in semiconductor technologies, including ASICs and FPGA products, as well as deep knowledge of specialized requirements across various sectors, including wireless infrastructure, military, automotive, industrial, and data center markets. More>
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