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SolvNetPlus
Training & Education
Meta’s Success Story: Shift-Left: Accelerating Design Quality with Early Connectivity Checks
Connectivity errors in complex SoC designs can be difficult to detect and costly to fix when discovered late in the design cycle. In this session, Meta shares how it adopted a shift-left verification strategy using Synopsys VC SpyGlass™ Connectivity to automate connectivity validation at the RTL stage. Through advanced connectivity checks and integration into continuous integration workflows, the team improved design quality, accelerated debug, and reduced costly rework. Attendees will also see how these methodologies support broader DFT and TestMAX™-driven verification objectives in complex SoC development flows.
What You'll Learn
- How to implement a shift-left strategy for connectivity verification at the RTL stage
- The role of path checks and value checks in validating complex SoC connectivity and DFT requirements
- Advanced techniques for verifying connectivity at scale, including conditional checks, macros, and sequential-depth analysis
- How automated connectivity validation supports TestMAX testability goals and improves RTL quality
- Proven strategies for reducing ECOs and accelerating time-to-closure in complex SoC designs
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Featured Speakers
Anshul Bansal
Lead Implementation Engineer
Anshul Bansal is a Lead ASIC Engineer at Meta, currently serving as the Lead Implementation Engineer for the Meta Training and Inference Accelerator (MTIA) program. He oversees the physical realization of custom AI silicon across multiple hardware generations, with a specific focus on advanced process nodes down to 2nm. His work involves managing the practical trade-offs of power, performance, and area (PPA) while driving logic synthesis, timing closure, and process variation to ensure reliable silicon for large-scale AI infrastructure.
Swetha Karusala
ASIC Engineer
Swetha Karusala is an ASIC Engineer in Meta’s Infrastructure organization, working on the development of next-generation AI accelerators. A semiconductor industry veteran with over 13 years of experience, she specializes in end-to-end RTL-to-GDS execution for complex SoC designs. Prior to Meta, Swetha spent more than a decade at Intel, leading efforts in low-power clocking architectures, floorplanning, and static timing closure on advanced technology nodes. She holds an M.S. in Electrical and Computer Engineering from The Ohio State University.
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