Designing for RISC-V Success: Addressing the Triple Threat in ASSP Development

As System-on-Chip (SoC) designs grow in complexity, delivering great products requires early access of workload performance analysis to enable hardware/software co-design, pre-silicon. This presentation examines how MIPS, through its Atlas Explorer platform, empowers engineering teams to tackle the “triple threat” of custom SoC development: design complexity, performance validation, and resource optimization.

• Traditional methods struggle to keep pace with increasing architectural complexity. When modeled in Atlas Explorer, MIPS RISC-V-based platform IP is available for evaluation and performance analysis, well before RTL. This industry first increases workload performance and increases confidence for product market fit.
• To meet performance targets, engineers must make informed processor and system architecture decisions, and enable robust debug and test capabilities. With a combination of instruction accurate simulation and microarchitectural modeling, Atlas Explorer empowers developers to evaluate application performance early, compare processor options, and make optimization decisions based on detailed execution data.
• Atlas Explorer allows for early and secure engagement between IP providers and chip designers by using microarchitectural simulation, enabling real-world performance analysis without exposing proprietary software or design details. This opens opportunities for late-stage design decisions based on actual workloads and seamless collaboration across distributed teams through containerized, reproducible development environments.

By leveraging early, specification-driven modeling and co-development workflows, MIPS provides a comprehensive path to application-specific standard product (ASSP) success helping customers navigate the complexity of modern SoC design, confidently meet performance goals, and differentiate through full-stack optimization.