EDA
System
IP
SolvNetPlus
Training & Education
Cisco’s Success Story: Advancing HSAT Structural Test: PCIe Gen4 & Link Scale on ATE
Structural test data volumes continue to increase, placing new demands on test access bandwidth and efficiency. In this session, Cisco shares its experience deploying Synopsys HSAT IP using PCIe Gen4 and Advantest Link Scale™ to enable high-speed scan access, streamline test operations, and support structural test from pre-silicon verification through silicon bring-up. Attendees will gain insight into the end-to-end deployment process and proven strategies for successfully deploying scan-over-HSIO solutions in production semiconductor environments.
What You'll Learn
- Why advanced semiconductor designs are outgrowing traditional GPIO-based structural test access methods
- How Cisco leveraged HSAT and PCIe Gen4 to increase test bandwidth and improve test efficiency
- Key design and implementation considerations for integrating HSAT into complex SoC environments
- Practical approaches for ATPG pattern generation, verification, simulation, and emulation using HSAT
- Real-world experiences from silicon bring-up, test deployment, and failure diagnosis using high-speed test interfaces
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Featured Speaker
Chuanyun Fan
Chuanyun Fan is a director of engineering at Cisco Systems of the design-for-testability (DFT) team contributing to Cisco ASIC and Silicon One chips. He leads DFT architectures and methodologies for production screening, in system structure testing, and failure diagnosis.
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