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Training & Education
Arm's Success Story: SLM Implementation on Arm Cores
Bringing silicon observability into a high-performance CPU isn't just about dropping in sensors—it requires careful decisions around coverage, timing, clocking, physical design, and implementation overhead. In this session, Arm shares its first deployment of Synopsys Path Margin Monitor (PMM) IP in Arm cores, offering an inside look at the challenges, tradeoffs, and results from integrating embedded timing monitors into a production-class CPU design.
What you'll learn:
- Why traditional monitoring approaches can leave blind spots in advanced CPU designs—and how PMMs help fill the gap.
- The methodology Arm used to deploy PMMs across a large hierarchical core while maintaining implementation efficiency.
- How coverage goals were balanced against timing closure, routing resources, and area constraints.
- Practical solutions for managing clocking, skew, and integration challenges during deployment.
- What the final design metrics reveal about the overhead, observability, and optimization opportunities enabled by embedded timing monitoring
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Featured Speakers
Pratap Machineni
Staff Engineer
Pratap Machineni is Staff Engineer at Arm Limited. focused on methodology and PPA improvements as part of DTCO. His background includes expertise in physical design from synthesis to GDSII, Timing and PDN signoff. He also guides collaborative development in EDA flows, PPA scaling, and other SOC activities.
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