Intel Accelerates Memory Subsystem Validation with a Reusable Framework

As AI-driven and data-intensive systems place greater demands on memory subsystem validation, engineering teams require scalable approaches to support DDR, LPDDR, and HBM technologies while maintaining high productivity.

This success story explores how Intel addressed validation bottlenecks caused by fragmented, project-specific transactor implementations by partnering with Synopsys to create a standardized and reusable framework based on Synopsys DFI Transactors.

Learn how a structured methodology spanning integration, validation, deployment, and automation improved consistency, reduced maintenance effort, and enhanced debug efficiency through greater observability into memory subsystem behavior.

The presentation will demonstrate how this approach delivered a 2.5× increase in validation throughput, reduced bring-up and debug time by 3x, and enabled successful reuse across multiple programs, creating a scalable foundation for next-generation memory validation.

What You Will Learn
 

• How to implement a standardized validation infrastructure for DDR, LPDDR, and HBM memory technologies using Synopsys DFI Transactors.
  
  
• Best practices for creating reusable validation and debug methodologies that can be deployed across multiple IP and SoC programs.
  
  
• How enhanced observability and analysis capabilities can accelerate root-cause analysis and improve bring-up efficiency.
  
  
• Lessons learned from achieving a 2.5x improvement in validation throughput and a 3x reduction in bring-up and debug time through framework standardization and reuse.