Accelerating Coverage Closure with AI-Based Verification Space Optimization

Coverage is at the heart of all modern semiconductor verification. There is no maxim more fundamental to this process than “if you haven’t exercised it, you haven’t verified it.” Although covering a particular aspect of a chip design does not guarantee that all bugs are found—bug effect propagation and checker quality are also key factors—it is certainly true that bugs cannot possibly be triggered in logic that has not been exercised. Coverage is often regarded as a proxy for finding bugs and is therefore a key focus for verification using simulation-based testing.