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Synopsys Pipelined AES-XTS IP Datasheet
The Synopsys Pipelined AES‑XTS Core datasheet describes a silicon‑proven encryption IP implementation of the de-facto cryptographic algorithm for protecting the confidentiality of data-at-rest on storage devices. It enables high‑throughput and is fully compliant with the IEEE 1619‑2007 specification. This configurable AES‑XTS implementation delivers up to 64 Gbps of throughput while balancing performance, gate count, and integration flexibility for modern disk and solid‑state storage applications.
What You Will Learn:
- How AES‑XTS encryption protects data‑at‑rest against cut‑and‑paste and tampering attacks
- How configurable pipeline options optimize throughput versus gate count
- How support for 128‑bit and 256‑bit AES keys meets evolving storage security requirements
- How silicon‑proven AES‑XTS IP scales to SATA, SAS, Fibre Channel, and high‑speed SSD designs
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