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Smarter Metrics, GPU Scale, and AI-Driven Workflows for Computational Lithography
At advanced nodes, observed defectivity, variability, and process-window behavior increasingly extend beyond what EPE and CD metrics can characterize. Closing that gap requires new ways to model, optimize, and measure patterning as well as the GPU and AI-driven scale to deploy them on production timelines. Join Synopsys lithography experts to see what comes next.
Why Attend
- Move beyond EPE-only thinking to cost functions that are defectivity-aware, process-window driven, and topology-constrained to balance competing manufacturing goals.
- Measure what CD and registration miss — contour-based EPE analysis for curvilinear patterns, variation, OPC/ILT correction quality, and overlay.
- See GPU acceleration in production terms — faster turnaround, lower cost of ownership, and practical rigorous 3D simulation and ML-enabled modeling.
- Put agentic AI to work — Knowledge Assistants and Mask Space Optimization (MSO)that speed recipe generation, troubleshooting, and deployment.
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Detailed Agenda
Thuc Dam
Sr. Director of Applications Engineering
Next-Generation ILT: Advanced Cost Functions for Manufacturing Challenges and GPU Acceleration for Production Scalability
11:00 PM PST | 8:00 AM CES | 3:00 PM TW | 4:00 PM KR/JP
As process nodes grow more complex, edge-placement metrics alone can no longer address defectivity, variability, and process-window challenges. This seminar will show how Inverse Lithography Technology (ILT) is evolving through richer cost functions—defectivity-aware models, process-window optimization, and topology-based constraints—that balance competing manufacturing goals, and how GPU acceleration makes these methods practical in production by reducing turnaround time and cost of ownership at advanced nodes.
Germain Fenger
Sr. Director of Product Management
Comprehensive Contour-Based Metrology for Patterning and Process Qualification
11:30 PM PST | 8:30 AM CES | 3:30 PM TW | 4:30 PM KR/JP
As patterning complexity increases, traditional CD and registration metrics cannot fully capture two-dimensional pattern fidelity, local variation, or correction performance. This presentation will show how S-Metro applies contour-based EPE analysis to characterize curvilinear patterns and defects, classify variation, assess compact-model and OPC/ILT correction quality, and evaluate overlay; enabling data-driven patterning and process qualification.
Larry Melvin
Sr. Director of Technical Product Management
GPU-Enabled Innovation for Next-Generation Lithography
12:00 AM PST | 9:00 AM CES | 4:00 PM TW | 5:00 PM KR/JP
GPUs are transforming lithography by delivering more than faster computation—they are making previously impractical modeling and optimization capabilities accessible for production use. This presentation will highlight how GPU acceleration advances applications such as rigorous 3D simulation, machine-learning-enabled modeling, and Aurora by improving turnaround time, increasing computational scalability, and enabling solutions that would otherwise be too computationally expensive for practical deployment.
Brian Ward
Principal Engineer and Technical Product Manager
Advancing Lithography Engineering with Agentic AI: Streamlining Workflows for Faster Deployment
12:30 AM PST | 9:30 AM CES | 4:30 PM TW | 5:30 PM KR/JP
As lithography flows grow more complex, engineering teams face mounting pressure to deliver optimized, production-ready solutions faster with limited expert resources. This presentation will explore how Knowledge Assistants, Mask Space Optimization (MSO), and Agentic AI can improve lithography workflows. Attendees will learn how Synopsys is using these AI-driven capabilities to accelerate optimization, streamline tasks such as recipe generation and troubleshooting, and enable faster, more efficient deployment.
Meet the Speakers
| Presenter Name | Title / Company | About |
| Thuc Dam | Sr. Director of Applications Engineering | Thuc Dam holds a PhD in applied organic chemistry from UTD. He has worked in semiconductor field for 24 years with 30+ publications and 2 patents, and has previously been employed in technical and managerial roles at Intel and Luminescent Inc. His innovations in mask process development, ILT, SMO, and DRE have contributed extensively to the computational lithography domain. He is growing his experience in DTCO, AR/VR and EUV. He is currently the Sr Director of Applications Engineering for the ILT, PLRC & SMO groups at Synopsys. |
| Germain Fenger | Sr. Director of Product Management at Synopsys | Germain Fenger is a Sr. Director of Product Management at Synopsys, where he leads advanced mask solutions and computational lithography technologies. With a background spanning semiconductor manufacturing, lithography research, engineering, and product leadership, Germain has held roles at imec, GlobalFoundries, Mentor Graphics, Siemens EDA, and Synopsys. He holds a Ph.D. in Microsystems, has authored more than 80 publications, and holds multiple patents in the field. |
| Dr. Larry Melvin | Sr. Director of Technical Product Management at Synopsys | Larry Melvin is Sr. Director of Technical Product Management at Synopsys, with a career that spans X‑ray lithography research, fab‑level photolithography engineering, and advanced OPC and modeling. His current work focuses on mask modeling, high‑NA EUV, AR/VR, stochastics, and next‑generation digital‑twin data flows that improve performance and yield. Larry’s current passion is developing technology to help chip design and manufacturing interact to improve yield, performance, and area. |
| Brian Ward | Principal Engineer and Technical Product Manager at Synopsys | Brian Ward is a Principal Engineer and Technical Product Manager for AI and Agentic Systems at Synopsys. With more than 20 years of experience in computational lithography, modeling, metrology, OPC, and ILT, he now leads AI strategy across the Mask Solutions portfolio, focusing on Knowledge Assistants, Workflow Assistants, and Agentic AI technologies that help semiconductor engineers automate complex workflows and accelerate innovation. He holds B.S. and M.S. degrees in Electrical Engineering from The University of Texas at Austin. |