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Why Attend?
Join us for an exclusive Synopsys VC Formal Seminar where innovation meets execution. This event is designed for verification engineers, managers, and technology enthusiasts who want to stay ahead in the rapidly evolving world of formal verification.
What You’ll Discover
- End-to-End Proof Convergence – Solve complex problems faster
- Generative AI Driving Verification Breakthroughs – Automate and accelerate workflows
- Formal Advisor – Overcome proof blockers and achieve full convergence
Expert Sessions & Customer Insights
Explore what’s new in VC Formal and get a sneak peek into the future of formal verification technologies
End-to-end proof on a complex problem using ProofAssist and ProofArchitect
How AI and formal techniques accelerate signoff and improve design quality
Don’t miss this opportunity to connect, learn, and lead the future of verification.
Note: Due to limited seating capacity, registration requests will be reviewed upon submission.
Event Agenda
Agenda items are subject to change. Kindly refer back for any updates.
9:30 - 10:00
Registration Check-in
10:00 - 10:10
Welcome Address
10:10 - 10:25
Vision Talk on Formal Verification and AI
Manish Pandey - Synopsys
10:25 - 11:00
Synopsys VC Formal Technology Update
Sandeep Jana - Synopsys
11:00 - 11:15
Networking Break
Coffee + Demos = Productivity! Use your break to check out live demos.
11:15 - 11:45
Convergence and Checker Agent using GenFV
Bindumadhava S, Anirban Majumder - Google
11:45 - 12:15
AI‑Powered Formal for Complex Fabric Bridges with Modular FPV Signoff and E2E Bug Discovery
Sachin Kumawat - Microsoft
12:15 - 12:30
Novel Use of Symbolic Map Based Constraints for Synchronization Block Verification Using Formal Methods
Patnala Naga Sai - Qualcomm
12:30 - 1:30
Networking Lunch Break
While you enjoy lunch, don’t miss the Demo Station—your chance to explore Formal Advisor, FPV Signoff, Unified Debug, Proof Architect, and DPV Dynamic Orchestration.
1:30 – 2:00
Accelerating Formal Convergence Using GenFV
Sangamesh Kokatnur - Nvidia
2:00 - 2:30
Achieving High Confidence Convergence - A VC Formal Case Study
Rajib Lochan - Intel
2:30 - 3:00
From Guesswork to Guarantee Unifying Firmware with Formal Proofs
Disha Puri - Synopsys
3:00 - 3:20
Networking Break
3:20 - 4:05
Panel Discussion: AI Meets Formal - Redefining the Verification Frontier
4:05 - 4:20
Closing and Lucky Draw
Live Demo Experience
Explore the power of VC Formal through hands‑on, expert‑led demonstrations throughout the event. Our Live Demo Zone is designed to give you a closer look at the latest capabilities, workflows, and innovations that accelerate verification closure and improve design quality.
What's on Display:
- Formal Advisor
- FPV Signoff
- Navigator and unified debug for FPV
- Proof Architect
- DPV Dynamic Orchestration