Synopsys and Ansys power the future of innovation—connecting silicon to systems.
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Training & Education
Why Attend?
Synopsys is the world’s leading provider of solutions for designing and verifying advanced silicon chips. Join us at DVCon India 2026 to learn how we help customers optimize chips for power, performance, and cost, cutting months off their project schedules.
Keynote Session
Generative AI: Is it Real or Merely a Hallucination?
Speaker: Pallab Dasgupta, Vice President of R&D Engineering, Synopsys
Date & Time: September 2 | 9:30 – 10:00 AM
Generative AI is reshaping the landscape of design and verification, but separating genuine breakthroughs from hype remains a challenge. As artificial intelligence becomes increasingly embedded in our daily workflows—from voice assistants to autonomous systems—the question arises: is generative AI delivering real, practical value in chip design verification, or are we chasing illusions? And, with the advent of Large Language Models (LLM) and Generative Pre-Trained Transformer (GPT) models, what are the possibilities in design verification?
This session will examine the current state of generative AI in design and verification. We’ll explore where Synopsys is investing in agentic solutions and what technology is being implemented in production environments by end users, delivering significant productivity boosts and automation. Join us to discover whether generative AI is truly revolutionizing the industry—or if it’s still more hallucination than reality.
Synopsys Sessions
Tutorial: System Validation using Synopsys Interface Solutions
Presenters: Anunay Bajaj, Pradeep Kumar M P, Sairam Allu
Date & Time: September 1 | 11:15 - 12:45
Abstract:
Today’s conventional wisdom is that you need the fastest and highest capacity verification engines to tackle the hardware and software complexity of complex multi-die systems. Those teams who are just thinking about these aspects are in for a rough awakening! Without a full range of interface solutions matching the IP to their verification engines, they can spend months before they can run the 1st system validation test. Participants of this tutorial will learn what it takes to validate an interface with state-of-the-art solutions. We will highlight what interface solutions need to offer and how they are practically used and will share videos that demonstrate their application in detail.
Tutorial: Scalable Formal Verification in the Era of AI
Presenters: Sandeep Jana
Date & Time: September 1 | 14:00 - 15:30
Abstract:
As artificial intelligence systems become increasingly integrated into safety‑critical and mission‑critical domains, ensuring their correctness, robustness, and trustworthiness is a pressing challenge. Formal verification offers mathematically rigorous guarantees, but traditional techniques struggle to scale to the size, complexity, and data‑driven nature of modern AI systems. This tutorial explores the emerging landscape of scalable formal verification in the era of AI. We examine key challenges posed by deep learning models, probabilistic behavior, and learning‑enabled components, and survey recent advances that address scalability through abstraction, compositional reasoning, modular verification, and integration with data‑driven methods. We also highlight synergistic approaches that combine formal methods with AI techniques, such as learning‑assisted verification, neural abstractions, and automated invariant discovery. Finally, we discuss open research questions and future directions toward making formal verification practical and effective for large‑scale AI‑enabled systems, with the goal of improving reliability, safety, and societal trust in AI technologies.
Workshop: Design Faster, Debug Smarter: AI-Enhanced Verification
Presenters: Taruna Reddy
Date & Time: September 1 | 14:00 – 14:45
Abstract:
This session highlights breakthrough AI-powered advancements in debug workflows for RTL design and verification, featuring state-of-the-art capabilities of the Synopsys Verdi platform. Attendees will learn how Verdi's intelligent technology leverages sophisticated artificial intelligence (AI) to enhance collaborative problem-solving, streamline data analysis, and facilitate multi-level debug across simulation, emulation, formal, and static verification environments. Integration with Synopsys verification tools and popular development environments enables users to interact with Verdi for a range of investigative and diagnostic tasks.
Exhibit Booth
Visit the Synopsys booth to discover our comprehensive verification solutions spanning AI enhanced simulation, advanced debug, static and formal verification, emulation, FPGA-based prototyping, and virtual prototyping. See the HAPS prototyping system and interface daughter cards on display, and learn how teams are accelerating software development, system validation, and pre-silicon bring-up using the latest ZeBu-200 and HAPS-200 platforms. Connect with our experts to explore scalable hardware-assisted verification strategies and accelerate software and system validation earlier in the development cycle.