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SNUG Korea 2026 Proceedings

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Agenda

Theme: Re-Engineering The Future

Topic
[Keynote 1] Re-engineering the Future of Silicon Design Shankar Krishnamoorthy / Chief Product Development Officer of Synopsys
[Keynote 2] The Future of Agentic AI and Innovations in the HBM–HBF–HBS Memory Hierarchy Prof. Jungho Kim of KAIST
[Keynote 3] Paving the way for Silicon Intelligence Ben(Hyo Gyuem) Rhew, Corporate VP, Samsung Foundry
[Keynote 4] Building a New Memory and Storage Hierarchy for AI Inference SangKyoo Jeong, SVP, SK hynix
[Keynote 5] From LLMs to Agentic and Physical AI: Where AI Models Are Headed and What They Demand from Silicon Prof. Jinwoo Shin, KAIST
AI-Powered Design Optimization	Multi-Die and Next-Generation Memory	AI-Driven Silicon Innovation	Scalable Verification for AI Chip Era	Shift-Left Manufacturing Design
Systematic Exploration of Design Variations using Parametric Scenario Extension (PSX)	Multi-Die Prototyping, Bump Planning, and SI Analysis (with Demo)	Using Synopsys.ai Copilot in Fusion Compiler Platform	Maximizing the benefits from Software-defined Hardware-assisted Verification	TCAD Trend and Update
Jaewon Jung , Synopsys	Misun Lim, Synopsys	Sooyeon Kim, Synopsys	Kangwook Lee, Synopsys	Kartik Venkataraman, Synopsys
Achieving Signoff Confidence with IR-Aware STA	The X-section optimization of 2.5D signal routing with 3DSO	Agentic AI & Analog, AI driven Analog	Pre-Silicon Real Workloads Validation : Integration of Wireless Network Testers on ZeBu	Overcoming DUV Patterning Challenges with ArF Immersion Extensions
Dooha Kim, Samsung	Hyemin Kim, Samsung	Yuval Shay, Synopsys	Kyuho Shim, WooYoung Noh, Samsung	Bongkeun Kim, Samsung
AI-Driven Floorplan Exploration for Chip-Size Reduction with DSO.ai	Scaling Timing Signoff for Advanced Node and Multi-Die Designs: Signoff Tutorial - PrimeClock	Analog Layout Synthesis: A new Paradigm to Accelerate Analog Design	Reinforcement Learning–Based Optimization of SoC Performance Parameters on the ZeBu	From Silicon to Systems: Synopsys and NVIDIA Accelerated Engineering
Jonghyeop Kim, Samsung	Chul Rim, Synopsys	Donghee Kim, Synopsys	Hyungtae Park, Samsung	Kihang Youn, NVIDIA
Improving ATPG Debug Productivity Through Hold-Time Diagnosis	Analysis of PDN in 12-High HBM 3DIC for Heterogeneous Integration	Chiplets for AI Data Centers: Shift-Left, 3DIC Integration, and Co-Packaged Optics	ZeBu - SpeedAdaptor3 solution for CXL 3.x memory	TCAD application use-case
Doyeon Hwang, Samsung	Jiwoo Hong, Samsung	Ravi Todi, Synopsys	Minsu Yu, Samsung	Namki Cho, Synopsys
Physics-Aware CNN-Based IR Drop Risk Prediction for Fast and Reliable SRAM Placement Optimization	Thermal Analysis Workflow Introduction from On-Chip to PKG	Solving the Al Compute-to-l/O Gap with Scalable Interface IP	VC Z01X - Manufacturing Fault Simulation	Invited talk : Physics-Informed Graph Neural Surrogate for TCAD
Seihyung Jang, SK hynix	Steven Choi, SangJae Park, ADTechnology	Manmeet Walia, Synopsys	SeongWook Lee, Samsung	Yoon Kim, Synopsys with SK hynix
Low Power Optimization through Fast and Accurate Time-Based Power Analysis	ML-Based Sigma Av–aware Switch Cell Optimization	Addressing Physical AI Application Challenges with Standards-Based IP	Technology Overview: Advancing Analog, Mixed-signal, and RF Designs	Computational Lithography Trends in the AI Era
Sora Park , Samsung	Sungsu Byun, Samsung	Mehak Kalra, Synopsys	Yuval Shay, Synopsys	Al Blais, Synopsys
Product test pattern count reduction from ATPG configuration optimization with TSO.ai	Accelerating Signoff TAT with HyperScale/HyperGrid and PrimeClosure	Advanced PVT Monitoring Solutions for N2P GAA Technology and AI Workloads	Shift-Left Digital Twin with Virtual Prototyping	Invited talk : Interface physics and contact engineering for 2D FETs using QuantumATK
Jaeseok Park, Samsung	Deok-keun Oh, Samsung	Sehee Han, Synopsys	Ingwang Chang, Synopsys	Prof. Changwook Jeong, UNIST

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