View SNUG India Keynotes

Keynote: Re-engineering the Future of Silicon

The opening keynote presentation from Ravi Subramanian, Chief Product Management Officer of Synopsys focused on Re-engineering the future of India’s engineering.

Keynote: The AI Silicon Puzzle: From Transistors to Trillion-Parameter Systems 

Explore how AI is reshaping silicon infrastructure—from compute and memory to advanced packaging and power efficiency. Dr. Paul Rousseau, Vice President, Field Technical Solutions Division of TSMC shares insights on scaling AI to trillion-parameter systems and the need for ecosystem-wide co-design and innovation.

Keynote: Bringing Intelligence to the Edge: Into the world of SDVs and Physical AI 

Explore how Physical AI is driving intelligence to the edge—from AI-defined vehicles to real-time decision-making systems. Amardeep Punhani, Sr. Director, R&D of NXP Semiconductors shares how scaling and optimizing AI is enabling smarter, more autonomous applications.

Re Engineering Automotive and Physical AI Development: From Chips to Intelligent Systems with Virtual Engineering, Digital Twins, and AI 

Learn how virtual engineering, digital twins, and AI are reshaping automotive and Physical AI development through a unified silicon-to-systems approach. A G Raghunath, Executive Director, R&D, Synopsys, shares how “virtual-first” workflows accelerate innovation, reduce risk, and improve time to market.

Keynote: The Future of Rack-Scale AI Infrastructure 

A deep dive into how next-gen AI infrastructure is evolving to address performance, memory, and connectivity challenges at scale. Dr. Shivananda R Koteshwar, Senior Vice President and Managing Director, Astera Labs, shares insights on enabling flexible, high-performance rack-scale AI systems.

Bridging the Al Compute-to-l/O Gap with Scalable Interface IP 

Understand how evolving AI workloads are driving new demands on memory, die-to-die, and SerDes interfaces to overcome system bottlenecks. Madhumita Sanyal, Sr Director, Technical Product Management, Synopsys, highlights how advanced interface IP enables higher bandwidth, lower latency, and power-efficient AI systems at scale.

Keynote: Packaging Keeps Moore’s Law Scaling Going 

Gain insights into how advanced packaging and heterogeneous integration are extending Moore’s Law beyond transistor scaling. Arun Chandrasekhar, Sr. Principal Engineer, Intel, and Satish K Surana, Senior Principal Engineer, Intel, discuss multi-die design challenges, 3DIC verification, and best practices for scalable, high-performance systems.Keynote: Packaging Keeps Moore’s Law Scaling Going 

Enabling AI Factories: Scalable Multi-Die Advanced Packaging Design

See how multi-die integration is powering next-gen AI and HPC systems through advanced packaging and system-level optimization. Padmesh Mandloi, Vice President, Application Engineering, Synopsys, shares how unified design platforms and AI-driven workflows help manage complexity and accelerate scalable, high-performance designs.Enabling AI Factories: Scalable Multi-Die Advanced Packaging Design

Scaling Intelligence at the Edge: Silicon Innovation for Vision Driven, AI Enabled Consumer Systems 

A perspective on how advanced silicon, IP, and AI-driven design are enabling next-gen edge and vision-based applications. Ritesh Goel, Senior Architect of Hardware Assisted Verification Solutions, Synopsys, highlights how scalable platforms accelerate development and deliver high-performance, power-efficient consumer systems.