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SNUG 中国 2018
SNUG 2018 论文集
技术委员会获奖论文（winners list）
一等奖
Reduce MBIST Area Using Shared Wrapper
二等奖
Useful Skew Enhancement for Timing Closure with IC Complier II
Using VC Formal to Do DFT Clock Verification
三等奖
RTL Improvement for Placement and Routing
Using VC-APPs to Boost Verification and Debug Efficiency
入围论文
A Synthesized and Consistent Clock Management Solution Covering Full Pre-silicon Steps
Analysis X Source by Using SpyGlass DFT
Benefit from HyperScale Flow at Timing-closure Stage
Block Level Clock Tree Improvement
Hierarchical SOC Design Implemented by ICC II
Implementation of H-tree Clock Structure in Module with ICC II
Improving ATPG Efficiency with SpyGlass DFT in Customerized Flow
Improving Timing Convergence between ICC II and PrimeTime for 7nm design Signoff
Latch Array Implementation with Relative Placement in IC Compiler II
Using VC Formal to Check SOC Level Connections and Coverage Analyze
SNUG 2018 上海 各论坛演讲资料分享：
1. Mobile Computing & High Performance Computing
Emerging Node Design with IC Compiler II
56G and 32G SerDes Enables Cloud Computing Applications with 100G/200G Ethernet and PCIe 5.0
What Advanced Node Support Means to Synthesis, What’s Changing and What it Promises to Deliver
Block Level Clock Tree Improvement
Benefit from HyperScale Flow at Timing-closure Stage
Design and Verification Considerations for 5G SoC
4. Automotive
Test Interaction with Functional Safety
ADAS SW development and integration on a Virtual Prototype at NXP and 1st Tier
What’s Required for Safety-Critical Semiconductor Designs?
Accelerating Automotive ADAS SoC Development with ASIL Certified IP
Automotive - Functional Safety Verification
Memory Test & Repair and Hierarchical Test of Interface IP for Automotive FinFET based SoC’s
SNUG 2018 北京 各论坛演讲资料分享：
1. Mobile Computing & High Performance Computing
2. IoT & Low Power
Next Generation Signoff Power and Reliability Analysis – Introduction and Tutorial
FastSpice – What’s New & The Application of Monte-Carlo in Mixed-Signal Simulation
What Advanced Node Support Means to Synthesis, What’s Changing and What it Promises to Deliver
3. Advanced Modeling & Manufacturing
Accelerating Robust Custom Design
7-nm Design Tips for Performance, Power & Area Optimization
Custom Compiler Template-Based Design for Layout Automation
Physically-Aware Simulation and Electrical Analysis During with Fusion Technology
Industry Proven Solution to Achieve Fast Yield Ramp for New Products
4. Automotive
Test Interaction with Functional Safety
ADAS SW development and integration on a Virtual Prototype at NXP and 1st Tier
What’s Required for Safety-Critical Semiconductor Designs?
Accelerating Automotive ADAS SoC Development with ASIL Certified IP
Automotive - Functional Safety Verification
Memory Test & Repair and Hierarchical Test of Interface IP for Automotive FinFET based SoC’s