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Verifying CXL 3.1 Designs with Synopsys Verification IP

BLOG Apr 11, 2024/4 min read

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Verifying CXL 3.1 Designs with Synopsys Verification IP

By Zongyao Wen, Nikhil Jain

Tags: Engineering Central, Verification IP, Verification

Nikhil Jain

Nikhil Jain is a Principal Product Engineer at Synopsys. Nikhil has worked on Verification IP for 16+ years. Nikhil works on the development of CXL, NVMe over fabrics, Memories, and Ethernet products and VIP technologies.

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