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Shift‑Left SoC Performance Analysis: De‑Risking Cache‑Coherent RISC‑V SoCs
As high-performance computing (HPC) SoCs grow in complexity, architecture teams need the ability to evaluate design choices and identify bottlenecks before RTL development begins. Openchip presents how Synopsys Platform Architect enables executable system modeling, real Linux workload execution, and workload-driven performance analysis to accelerate architectural decisions, reduce risk, and optimize next-generation RISC-V HPC platforms.
What You Will Learn
- How Openchip uses Platform Architect to de-risk HPC SoC development by creating executable models that enable architectural validation and performance analysis long before RTL is available.
- How workload-driven exploration improves architecture decisions through real Linux workload execution and detailed analysis of cache, NoC, memory, and system-level interactions.
- How early hardware-software co-optimization accelerates development by identifying bottlenecks sooner, reducing costly redesigns, improving software readiness, and shortening design evaluation cycles.
Watch On-Demand
Featured Speakers
Cristobal Ortega
Openchip
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