Micron Breaks the Memory Wall with 3X Faster Emulation Performance

As AI, data center, and software-defined systems continue to increase in complexity, Micron faces challenges to validate complete hardware and software systems for memory subsystems, including high-capacity NAND, HBM, and LPDDR memories.

This success story will explore how Micron addressed memory subsystem bottlenecks in its hardware-assisted verification environment by leveraging Synopsys ZeBu emulation and memory transactor technology to improve memory modeling efficiency and system-level performance.

Learn how Micron optimized data movement, increased parallelism and pipelining, and adopted a data-driven performance analysis methodology to overcome the "memory wall" that was limiting verification throughput.

The presentation will highlight the techniques that enabled more than a 3X improvement in emulation performance, accelerating software bring-up, improving system validation efficiency, and reducing development risk before first silicon.

What You Will Learn

• How to identify and eliminate memory subsystem bottlenecks that limit hardware-assisted verification performance.
  
  
• Best practices for optimizing data movement, caching, and host-memory interactions using Synopsys ZeBu memory transactor technology.
  
  
• Techniques for improving verification throughput through parallelism, pipelining, and performance-driven design optimization.
  
  
• How profiling and runtime analysis can be used to achieve significant emulation performance gains and accelerate software readiness before silicon availability.