Synopsys RISC-V Processor Verification Solutions Demo

Join this engaging live demonstration to see how Synopsys leading verification solutions ImperasDV, VCS Simulation and Verdi Debug tools can help you achieve TTM, improve engineering efficiency and release high quality RISC-V processor core

Agenda: 

• Introduction to RISC-V processors and growth of RISC-V Verification

• Introduction to Synopsys Imperas RISC-V Verification solutions

• Complete demo of ImperasDV RISC-V Verification IP with Synopsys VCS and Verdi debug solutions

Speaker:

John Taylor - Senior Director of Product Management

Jon has over 20 years of experience in the semiconductor industry, working in technical areas from CPU verification to embedded software, and commercial areas including field applications and technology strategy. He has worked on multiple architectures including Arm, RISC-V and proprietary CPUs. He holds a degree from Southampton University in Electronic Engineering and is currently Senior Director of Product Management at Synopsys working on technology to help enable the RISC-V revolution.