Siddartha Papineni

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Don’t Take the Risk, Formally Verify Your RISC-V Cores

WEBINAR May 25, 2023

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Don’t Take the Risk, Formally Verify Your RISC-V Cores

Featuring Siddartha Papineni

Sid Papineni is a Sr. Staff Applications Engineer at Synopsys and works on formal verification consulting services and Synopsys VC Formal SEQ, DPV, and product engineering activities. Sid has 11+ years of experience in the formal verification domain, focused mainly on formal property verification and datapath validation methodologies.

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