EDA
System
IP
SolvNetPlus
Training & Education
WEBINAR
Apr 20, 2023
From this Author
Maria Auras-Rodriguez
Maria joined the ASIP Designer R&D Team in 2019 where she focuses on the ASIP Designer’s HDL Generator tool, including synthesis support for ASIPs. She has a master's degree in Embedded Systems Design from ALaRI, University of Lugano. Before joining Synopsys, she worked as a researcher at the Institute for Communication Technologies and Embedded Systems (ICE) at RWTH Aachen University.
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