Synopsys ARC nSIM
The Synopsys ARC® nSIM Instruction Set Simulator provides an instruction accurate processor model for the Synopsys ARC processor families. Such processor models take the software development out of your products’ critical path by enabling an early start as well as increased efficiency through enhanced visibility and control. The nSIM models provide a complete and accurate hardware/software interface model of the ARC processors that guarantees binary compatibility of product code between the simulation platform and the hardware. The model is configurable and supports all the ARC processor families, ranging from the high-speed ARC HS Family and the deeply embedded ARC EM Family to the general-purpose ARC 600 Family and the ARC 700 Family for high-performance applications, as well as the ARC AS200 audio processors.
The nSIM Pro simulator comes with a state-of-the-art JIT compilation engine that leverages the capabilities of multi-core simulation hosts by offloading JIT translation threads from the core that is running the simulation reducing the JIT compilation overhead and significantly speeding up simulation performance. Embedded Microprocessor Benchmark Consortium (EEMBC) benchmarks on a simulation host running at 3.47 GHz show an 18X speed increase, on average, when JIT mode is activated and JIT translation is offloaded to a separate core of the simulation host. As a result, an average performance of 475 MIPS is reached across all 34 tests of the test suite. And over 1,400 MIPS is reached for the EEMBC bezier01 test that benefits most of the JIT activation.
In the case where a full 100% cycle accuracy is needed for final performance tweaking or verification, an ARC xCAM model can be used. These models are derived from the processor's Verilog to achieve 100% cycle accuracy.
| Interpretive | JIT | |
|---|---|---|
| Average speed | 20 MIPS | 475 MIPS |
| Instruction accuracy | 100% | 100% |
| Cycle accuracy | N/A | N/A |
| Software development & debug | YES | YES |
The nSIM processor model is delivered as a single DLL that integrates seamlessly with the MetaWare and GNU debuggers. The nSIM models come with an industry-standard OSCI TLM-2.0 SystemC interface to support their integration with OSCI standard peripheral models. In addition, the nSIM models implement the required interfaces for deployment in the Synopsys Virtualizer platform, a tool for the creation, assembly and execution of SystemC-based virtual prototypes for pre-silicon software development and software-driven verification.
nSIM Pro also includes the ARC HS38 Virtualizer Development Kit (VDK) for early software development ahead of silicon availability. It contains a reference virtual prototype with a dual-core ARC HS38 and system peripherals, a pre-built Linux image, sample Linux applications and is supported by ARC MetaWare and GDB Debuggers.
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- Single model supporting the ARC HS, ARC EM, ARC 600, ARC 700 and ARC AS200 families
- OSCI TLM-2.0 SystemC standard interface for integration with OSCI standard peripheral models
- Virtualizer integration layer provide access to advanced debugging and profiling capabilities offered by Virtualizer
- Very high speed JIT mode: 475 MIPS simulated performance for the EEMBC test suite on the ARC nSIM model for the ARC EM family
- Available for 64 bit Windows and Linux simulation hosts
- Models for EIA processor extensions and custom instructions can be added as an extension DLL or as a separate SystemC component
| Description: | ARC nSIM Instruction Set Simulator for ARC Processors |
| Name: | dw_arc_nsim |
| Version: | U-2023.03 |
| ECCN: | 3E991/NLR |
| STARs: | Open and/or Closed STARs |
| myDesignWare: | Subscribe for Notifications |
| Product Type: | DesignWare Cores |
| Documentation: | |
| Download: | arc_nSIM |
| Product Code: | 3355-0, 6782-0, 6787-0, 8111-0, 8112-0, 9217-0, 9500-0, A412-0, E035-0, F604-0 |