DesignWare IP Solutions for PCI Express 

DesignWare IP Solutions for PCI Express

Overview 

Synopsys’ complete, silicon-proven DesignWare® IP for PCI Express® (PCIe®) solution includes a suite of digital controllers, PHYs, and verification IP, all of which are designed to the PCIe 4.0, 3.1, 2.1 and 1.1 (Gen4, Gen3, Gen2, Gen1) and PIPE specifications. In addition, Synopsys supports the M-PCIe™ ECN with silicon-proven M-PHY and M-PCIe Controller IP. As the leading supplier of PCIe IP, Synopsys’ DesignWare IP for PCIe® has gone through extensive third-party interoperability testing with products shipping in volume production. The strict quality measures combined with an expert technical support team enables designers to accelerate time-to-market and reduce integration risk for next-generation mobile, consumer, communication, enterprise, IoT and automotive system-on-chips (SoCs).

More than 1,000 customers use DesignWare IP for PCI Express in their SoCs. See why Synopsys is the Trusted PCIe IP Partner.

PDF Complete DesignWare IP Solution for PCI Express
View all DesignWare IP for PCI Express Videos
 
  • PCI Express 4.0
  • Complete, silicon-proven IP solutions supporting the 16GT/s PCIe 4.0 spec 

Endpoint IP
Implements the port logic required for a PCIe Endpoint and supports the PCIe 4.0 and PCI-SIG SR-IOV specifications
PDF DOWNLOAD DATASHEET (PDF)


Root Port IP
Implements the port logic required for a PCIe Root Complex and supports the PCIe 4.0 and PCI-SIG SR-IOV specifications
PDF DOWNLOAD DATASHEET (PDF)


Dual Mode IP
Implements the port logic required for both a PCIe Root Complex and Endpoint and supports the PCIe 4.0 and PCI-SIG SR-IOV specifications
PDF DOWNLOAD DATASHEET (PDF)


Switch Port IP
Implements the upstream or downstream port logic required for a PCIe Switch or Bridge and supports the PCIe 4.0 specification
PDF DOWNLOAD DATASHEET (PDF)


PCI Express to AHB Bridge
Allows the DesignWare PCIe port logic to bridge to the AMBA 2.0 AHB on-chip bus
PDF DOWNLOAD DATASHEET (PDF)


PCI Express to AXI Bridge
Allows the DesignWare PCIe port logic to bridge to the AMBA 3 AXI/4 AXI on-chip bus
PDF DOWNLOAD DATASHEET (PDF)


Single Root I/O Virtualization IP
Integrates quickly, easily into SoC designs with a user-friendly application interface and conservative timing for a wide range of ASIC and FPGA technologies
PDF DOWNLOAD DATASHEET (PDF)


PCIe 4.0 PHY IP
Multi-channel, high-performance PCIe PHY IP operating at 16 Gbps available for numerous processes and foundries
PDF DOWNLOAD DATASHEET (PDF)


M-PCIe IP
Scalable controller IP that implements the port logic required to build a Root Port, Endpoint, Dual Mode, or Switch device
PDF DOWNLOAD DATASHEET (PDF)


IP Prototyping Kits
Accelerate PCIe IP prototyping, software development and integration
PDF DOWNLOAD DATASHEET (PDF)


Interface IP Subsystems
Configurable, pre-verified IP solutions for rapid SoC integration
PDF DOWNLOAD DATASHEET (PDF)


Verification IP
VC VIP for PCIe acts as either a Root Complex or Endpoint with support for PCIe 4.0, PIPE, SerDes, all popular simulators and M-PHY; It includes optional source-based test suites and support for NVMe
PDF DOWNLOAD DATASHEET (PDF)

  • PCI Express 3.1
  • Complete, silicon-proven IP solutions supporting the 8GT/s PCIe 3.1 spec 

Endpoint IP
Implements the port logic required for a PCIe Endpoint and supports the PCIe 3.1 and PCI-SIG SR-IOV specifications
PDF DOWNLOAD DATASHEET (PDF)


Root Port IP
Implements the port logic required for a PCIe Root Complex and supports the PCIe 3.1 and PCI-SIG SR-IOV specifications
PDF DOWNLOAD DATASHEET (PDF)


Dual Mode IP
Implements the port logic required for both a PCIe Root Complex and Endpoint and supports the PCIe 3.1 and PCI-SIG SR-IOV specifications
PDF DOWNLOAD DATASHEET (PDF)


Switch Port IP
Implements the upstream or downstream port logic required for a PCIe Switch or Bridge and supports the PCIe 3.1 specification
PDF DOWNLOAD DATASHEET (PDF)


PCI Express to AHB Bridge
Allows the DesignWare PCIe port logic to bridge to the AMBA 2.0 AHB on-chip bus
PDF DOWNLOAD DATASHEET (PDF)


PCI Express to AXI Bridge
Allows the DesignWare PCIe port logic to bridge to the AMBA 3 AXI/4 AXI on-chip bus
PDF DOWNLOAD DATASHEET (PDF)


Single Root I/O Virtualization IP
Integrates quickly, easily into SoC designs with a user-friendly application interface and conservative timing for a wide range of ASIC and FPGA technologies
PDF DOWNLOAD DATASHEET (PDF)


PCIe 3.1 PHY IP
Multi-channel, low-power PCIe PHY IP operating at 8 Gbps available for numerous processes and foundries
PDF DOWNLOAD DATASHEET (PDF)


M-PCIe IP
Scalable controller IP that implements the port logic required to build a Root Port, Endpoint, Dual Mode, or Switch device
PDF DOWNLOAD DATASHEET (PDF)


IP Prototyping Kits
Accelerate PCIe IP prototyping, software development and integration


IP Virtualizer Development Kits
Software development kits for early software bring-up, debug and test


Interface IP Subsystems
Configurable, pre-verified IP solutions for rapid SoC integration
PDF DOWNLOAD DATASHEET (PDF)


Verification IP
VC VIP for PCIe acts as either a Root Complex or Endpoint with support for PCIe 3.1, PIPE, SerDes, all popular simulators and M-PHY; It includes optional source-based test suites and support for NVMe
PDF DOWNLOAD DATASHEET (PDF)

  • PCI Express 2.1
  • Complete, silicon-proven IP solutions supporting the 5GT/s PCIe 2.1 spec 

Endpoint IP
Implements the port logic required for a PCIe Endpoint and supports the PCI Express 2.1 and PCI-SIG SR-IOV specifications
PDF DOWNLOAD DATASHEET (PDF)


Root Port IP
Implements the port logic required for a PCIe Root Complex and supports the PCI Express 2.1 and PCI-SIG SR-IOV specifications
PDF DOWNLOAD DATASHEET (PDF)


Dual Mode IP
Implements the port logic required for both a PCIe Root Complex and Endpoint and supports the PCIe 2.1 and PCI-SIG SR-IOV specifications
PDF DOWNLOAD DATASHEET (PDF)


Switch Port IP
Implements the upstream or downstream port logic required for a PCIe Switch or Bridge and supports the PCIe 2.1 specification
PDF DOWNLOAD DATASHEET (PDF)


PCI Express to AHB Bridge
Allows the DesignWare PCIe port logic to bridge to the AMBA 2.0 AHB on-chip bus
PDF DOWNLOAD DATASHEET (PDF)


PCI Express to AXI Bridge
Allows the DesignWare PCIe port logic to bridge to the AMBA 3 AXI/4 AXI on-chip bus
PDF DOWNLOAD DATASHEET (PDF)


Single Root I/O Virtualization IP
Integrates quickly, easily into SoC designs with a user-friendly application interface and conservative timing for a wide range of ASIC and FPGA technologies
PDF DOWNLOAD DATASHEET (PDF)


PCIe 2.1 PHY IP
Multi-channel, low BOM cost PCIe PHY IP operating at 5 Gbps available for numerous processes and foundries
PDF DOWNLOAD DATASHEET (PDF)


M-PCIe IP
Scalable controller IP that implements the port logic required to build a Root Port, Endpoint, Dual Mode, or Switch device
PDF DOWNLOAD DATASHEET (PDF)


IP Prototyping Kits
Accelerate PCIe IP prototyping, software development and integration
PDF DOWNLOAD DATASHEET (PDF)


IP Virtualizer Development Kits
Software development kits for early software bring-up, debug and test


Interface IP Subsystems
Configurable, pre-verified IP solutions for rapid SoC integration
PDF DOWNLOAD DATASHEET (PDF)


Verification IP
VC VIP for PCIe acts as either a Root Complex or Endpoint with support for PCIe 2.1, PIPE, SerDes, all popular simulators and M-PHY; It includes optional source-based test suites and support for NVMe
PDF DOWNLOAD DATASHEET (PDF)

  • PCI Express 1.1
  • Complete, silicon-proven IP solutions supporting the 2.5GT/s PCIe 1.1 spec 

Endpoint IP
Implements the port logic required for a PCIe Endpoint and supports the PCI Express 1.1 and PCI-SIG SR-IOV specifications
PDF DOWNLOAD DATASHEET (PDF)


Root Port IP
Implements the port logic required for a PCIe Root Complex and supports the PCI Express 1.1 and PCI-SIG SR-IOV specifications
PDF DOWNLOAD DATASHEET (PDF)


Dual Mode IP
Implements the port logic required for both a PCIe Root Complex and Endpoint and supports the PCIe 1.1 and PCI-SIG SR-IOV specifications
PDF DOWNLOAD DATASHEET (PDF)


Switch Port IP
Implements the upstream or downstream port logic required for a PCIe Switch or Bridge and supports the PCIe 1.1 specification
PDF DOWNLOAD DATASHEET (PDF)


PCI Express to AHB Bridge
Allows the DesignWare PCIe port logic to bridge to the AMBA 2.0 AHB on-chip bus
PDF DOWNLOAD DATASHEET (PDF)


PCI Express to AXI Bridge
Allows the DesignWare PCIe port logic to bridge to the AMBA 3 AXI/4 AXI on-chip bus
PDF DOWNLOAD DATASHEET (PDF)


Single Root I/O Virtualization IP
Integrates quickly, easily into SoC designs with a user-friendly application interface and conservative timing for a wide range of ASIC and FPGA technologies
PDF DOWNLOAD DATASHEET (PDF)


PCIe 1.1 PHY IP
Multi-channel PCIe PHY IP operating at 2.5 Gbps available for numerous processes and foundries
PDF DOWNLOAD DATASHEET (PDF)


M-PCIe IP
Scalable controller IP that implements the port logic required to build a Root Port, Endpoint, Dual Mode, or Switch device
PDF DOWNLOAD DATASHEET (PDF)


Interface IP Subsystems
Configurable, pre-verified IP solutions for rapid SoC integration
PDF DOWNLOAD DATASHEET (PDF)


Verification IP
VC VIP for PCIe acts as either a Root Complex or Endpoint with support for PCIe 1.1, PIPE, SerDes, all popular simulators and M-PHY; It includes optional source-based test suites and support for NVMe
PDF DOWNLOAD DATASHEET (PDF)

  • M-PCIe
  • Configurable IP for PCIe 4.0, 3.1, 2.1, 1.1, M-PCIe ECN, and RMMI specs 

M-PCIe
Scalable controller IP that implements the port logic required to build a Root Port, Endpoint, Dual Mode, or Switch device
PDF DOWNLOAD DATASHEET (PDF)


Endpoint IP
Implements the port logic required for a PCIe Endpoint and supports the PCIe 4.0, 3.1, 2.1, 1.1 and PCI-SIG SR-IOV specifications
PDF DOWNLOAD DATASHEET (PDF)


Root Port IP
Implements the port logic required for a PCIe Root Complex and supports the PCIe 4.0, 3.1, 2.1, 1.1 and PCI-SIG SR-IOV specifications
PDF DOWNLOAD DATASHEET (PDF)


Dual Mode IP
Implements the port logic required for both a PCIe Root Complex and Endpoint and supports the PCIe 4.0, 3.1, 2.1, 1.1 and PCI-SIG SR-IOV specifications
PDF DOWNLOAD DATASHEET (PDF)


Switch Port IP
Implements the upstream or downstream port logic required for a PCIe Switch or Bridge and supports the PCIe 4.0, 3.1, 2.1, 1.1 specifications
PDF DOWNLOAD DATASHEET (PDF)


PCI Express to AHB Bridge
Allows the DesignWare PCIe port logic to bridge to the AMBA 2.0 AHB on-chip bus
PDF DOWNLOAD DATASHEET (PDF)


PCI Express to AXI Bridge
Allows the DesignWare PCIe port logic to bridge to the AMBA 3 AXI/4 AXI on-chip bus
PDF DOWNLOAD DATASHEET (PDF)


M-PHY IP
Silicon-proven, low-power PHY IP with support for high-speed Gear 3 rates available in advanced process technologies
PDF DOWNLOAD DATASHEET (PDF)


Verification IP
VC VIP for PCIe acts as either a Root Complex or Endpoint with support for PCIe 4.0, 3.1, 2.1, 1.1, PIPE, SerDes, all popular simulators and M-PHY; It includes optional source-based test suites and support for NVMe
PDF DOWNLOAD DATASHEET (PDF)

Controller IP
  • Broad portfolio including Endpoint, Dual Mode, Root Port, and Switch/Bridge
  • Silicon proven; low latency and low gate count
  • Powers the Agilent and PCI-SIG protocol test card
  • Largest installed base of all PCI Express IP providers
PHY IP
  • Designed for integration of both upstream and downstream applications as well as PCI Express bridges and switches
  • Fully compliant with the PCI Express 3.x (8 GT/s), 2.x (5.0 GT/s), and 1.x (2.5 GT/s) as well as the PHY interface for PCIe 3.x (PIPE4 draft 6) (8-bit, 16-bit and 32-bit) specifications
  • Multi-tap adaptive continuous time linear equalizer (CTLE) and decision feedback equalization (DFE)
  • Extremely low in power consumption and size for smaller die area, improved jitter and sensitivity
Verification IP
  • Verifies all topologies of the controller including PCI Express endpoints, switches and root complex devices
  • Accelerates test development with built-in error injection and scoreboarding
  • Supports directed and constrained random traffic generation
  • Provides functional coverage of PCI Express transactions and coverage of the PCI Express compliance checklist


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