DesignWare Embedded Endpoint Controller IP for PCI Express

The DesignWare® Embedded Endpoint Controller IP for PCI Express® (PCIe®) implements a configurable and scalable embedded endpoint, while supporting all required features of the PCI Express 5.0, 4.0, 3.1, 2.1, 1.1 specifications. Using the DesignWare Embedded Endpoint Controller designers can implement an Endpoint downstream of a switch port within the same SoC, with no need for a physical link.

The high-quality, synthesizable IP is available in your choice of datapath widths, operating frequencies, and over 1200 configuration parameters, all working together to enable designers to optimize their applications for size, power, latency and throughput. The DesignWare Embedded Endpoint Controller IP for PCI Express integrates quickly and easily into system-on-chip (SoC) designs with a user-friendly application interface or an industry standard AMBA interface, and conservative timing suitable for a wide range of ASIC and FPGA technologies. It is an ideal solution to efficiently create a switch with embedded application logic and can be used together with the DesignWare Multi-Port Switch IP or with designers’ own switch architecture.

The DesignWare Embedded Endpoint Controller IP for PCI Express is based on the industry-leading DesignWare Controller IP for PCI Express that has been silicon validated in over 1600 designs with multiple hardware platforms, PHYs and PCIe verification suites, thereby reducing risk and improving time-to-market. As the industry standard for PCI Express, Synopsys offers a comprehensive IP solution that is in volume production and has been successfully implemented in a wide range of applications.

DesignWare Embedded Endpoint Controller IP for PCI Express Datasheet
DesignWare IP for PCI Express Complete Solution Datasheet

 

Highlights
  • Optimized, low-latency connection with Synopsys switch ports eliminates the need for a PIPE-to-PIPE interface, significantly reducing gate count and latency when building embedded PCI Express switches
  • Transparent to application software and Root Complex as an Endpoint connected to a downstream Switch Port
  • Supports all required features of the PCI Express 5.0 (32 GT/s), 4.0 (16 GT/s), 3.1 (8 GT/s), 2.1 (5 GT/s), 1.1 (2.5 GT/s) specifications
  • Supports Single-Root I/O Virtualization (SRIOV)
  • Application interfaces include the Synopsys native interface or the optional ARM® AMBA® 4 AXI and 3 AXI application interface
  • User-optimized configuration for low power, small area and low latency