DesignWare CXL Controller IP

The DesignWare® Compute Express Link (CXL) Controller IP implements the port logic required to build a CXL device or host, and can be configured for dual mode applications. The configurable and scalable IP supports all required features of the CXL 1.0 and 1.1 specifications, as well as PCI Express 5.0, 4.0, and 3.1 specifications, and can be easily connected to a DesignWare 32GT/s PHY through the built-in PIPE 5.2 interface. The high-quality, synthesizable IP is optimized for maximum throughput and minimum latency in a 32GT/s x16 configuration, but can be configured to support CXL port bifurcation and degraded modes, as well as all 3 defined CXL device types for maximum application flexibility. The DesignWare CXL Controller IP integrates quickly and easily into system-on-chip (SoC) designs with a user-friendly application interface or an industry standard AMBA interface on the CXL.io side, with conservative timing suitable for a wide range of ASIC and FPGA technologies.

The DesignWare CXL Controller IP is based on the Synopsys PCI Express controller IP which has been silicon validated in over 1700 designs with multiple hardware platforms, PHYs, and PCI Express verification suites, thereby reducing risk and accelerating time-to-market. As the industry standard for PCI Express, Synopsys offers a comprehensive IP solution that is in volume production and has been successfully implemented in a wide range of applications.

DesignWare Compute Express Link (CXL) Controller IP

Highlights

Products

Downloads and Documentation

Supports all features and performance requirements in the CXL 1.0 and 1.1 Specifications
Supports all required features of the PCI Express 5.0 (32 GT/s), 4.0 (16 GT/s), 3.1 (8 GT/s) and PIPE (32-bit) specifications
Application interface includes the Synopsys native interface with optional Arm® AMBA® 4 AXI and AMBA 3 AXI interface support for CXL.io
Based on silicon-proven 512-bit PCIe 5.0 controller design

CXL 1.1 Premium Controller Device/Host/DM 512b	STARs	Subscribe
CXL 1.1 Premium Controller Device/Host/DM 512b with AMBA bridge	STARs	Subscribe

Description:	CXL 1.1 Premium Controller Device/Host/DM 512b
Name:	dwc_cxl_11_prem
Version:	5.80a
STARs:	Open and/or Closed STARs
myDesignWare:	Unsubscribe
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Databooks DWC CXL Databook (5.80a) ( PDF \| HTML ) DWC PCIe DM Databook (5.80a) ( PDF ) DWC PCIe DM Databook - with Change Tracking (5.80a) ( PDF ) DWC PCIe DM Registers (5.80a) ( PDF \| HTML ) DWC PCIe DM Registers - with Change Tracking (5.80a) ( PDF ) DWC PCIe EP Databook (5.80a) ( PDF ) DWC PCIe EP Databook - with Change Tracking (5.80a) ( PDF ) DWC PCIe EP Registers (5.80a) ( PDF \| HTML ) DWC PCIe EP Registers - with Change Tracking (5.80a) ( PDF ) DWC PCIe RC Databook (5.80a) ( PDF ) DWC PCIe RC Databook - with Change Tracking (5.80a) ( PDF ) DWC PCIe RC Registers (5.80a) ( PDF \| HTML ) DWC PCIe RC Registers - with Change Tracking (5.80a) ( PDF ) DWC PCIe SW Registers (5.80a) ( HTML ) Datasheet DesignWare Compute Express Link (CXL) Controller IP ( PDF ) Doc Overview DWC PCIe Documentation Overview (5.80a) ( PDF ) Installation Guide DWC PCIe Installation Guide (5.80a) ( PDF ) Release Notes DWC PCIe Release Notes (5.80a) ( PDF ) Training Video Introduction to Buffering and RAMs Used in PCIe ( PDF ) User Guides DWC PCIe User Guide (5.80a) ( PDF \| HTML ) DWC PCIe User Guide - with Change Tracking (5.80a) ( PDF )
Toolsets:	Qualified Toolsets
Download:	dw_iip_DWC_pcie_ctl
Product Code:	E354-0

Description:	CXL 1.1 Premium Controller Device/Host/DM 512b with AMBA bridge
Name:	dwc_cxl_11_prem_amba
Version:	5.80a
STARs:	Open and/or Closed STARs
myDesignWare:	Unsubscribe
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Databooks DWC CXL Databook (5.80a) ( PDF \| HTML ) DWC PCIe DM Databook (5.80a) ( PDF ) DWC PCIe DM Databook - with Change Tracking (5.80a) ( PDF ) DWC PCIe DM Registers (5.80a) ( PDF \| HTML ) DWC PCIe DM Registers - with Change Tracking (5.80a) ( PDF ) DWC PCIe EP Databook (5.80a) ( PDF ) DWC PCIe EP Databook - with Change Tracking (5.80a) ( PDF ) DWC PCIe EP Registers (5.80a) ( PDF \| HTML ) DWC PCIe EP Registers - with Change Tracking (5.80a) ( PDF ) DWC PCIe RC Databook (5.80a) ( PDF ) DWC PCIe RC Databook - with Change Tracking (5.80a) ( PDF ) DWC PCIe RC Registers (5.80a) ( PDF \| HTML ) DWC PCIe RC Registers - with Change Tracking (5.80a) ( PDF ) DWC PCIe SW Registers (5.80a) ( HTML ) Datasheet DesignWare Compute Express Link (CXL) Controller IP ( PDF ) Doc Overview DWC PCIe Documentation Overview (5.80a) ( PDF ) Installation Guide DWC PCIe Installation Guide (5.80a) ( PDF ) Release Notes DWC PCIe Release Notes (5.80a) ( PDF ) Training Video Introduction to Buffering and RAMs Used in PCIe ( PDF ) User Guides DWC PCIe User Guide (5.80a) ( PDF \| HTML ) DWC PCIe User Guide - with Change Tracking (5.80a) ( PDF )
Toolsets:	Qualified Toolsets
Download:	dw_iip_DWC_pcie_ctl
Product Code:	E355-0