The Synopsys Compute Express Link (CXL) Controller IP implements the port logic required to build a CXL device, host or switch, and can be configured for dual-mode applications supporting runtime-selectability between device and host mode. The configurable and scalable IP supports all key required features of the CXL 3.0 specification and full backward compatibility with CXL 2.0, 1.0 and 1.1 specifications. The IP also supports PCI Express 6.0, 5.0, 4.0, and 3.1 specifications, and can be easily connected to a Synopsys 64GT/s PHY through the built-in PIPE 6.x interface. The CXL controller supports Synopsys' MultiStream architecture, offering multiple application interfaces for maximum throughput efficiency across various link widths and payloads. The high-quality, synthesizable IP is optimized for maximum throughput and minimum latency in a 64GT/s x16 configuration, but can be configured to support CXL port bifurcation and degraded modes, as well as all 3 defined CXL device types for maximum application flexibility. The Synopsys CXL Controller IP integrates quickly and easily into system-on-chip (SoC) designs with a user-friendly application interfaces or industry standard AMBA interfaces, with conservative timing suitable for a wide range of ASIC and FPGA technologies.
The Synopsys Integrity and Data Encryption (IDE) Security Modules for CXL
are standards-compliant and pre-verified with the Synopsys Controller IP to help designers protect data transfer in their SoCs against tampering and physical attacks. The security modules meet the required high bandwidth with optimal area and latency as low as zero cycles for CXL.cache/.mem protocols in skid mode.
The Synopsys CXL Controller IP is based on the Synopsys PCI Express controller IP which has been silicon validated in over 1800 designs with multiple hardware platforms, PHYs, and PCI Express verification suites, thereby reducing risk and accelerating time-to-market. As the industry standard for PCI Express, Synopsys offers a comprehensive IP solution in volume production and has been successfully implemented in a wide range of applications.
DesignWare Compute Express Link (CXL) Controller IP
Downloads and Documentation
- Supports all key features and performance requirements in the CXL 3.0, 2.0, 1.1 and 1.0 specifications
- Supports all required features of the PCI Express 6.0 (64GT/s), 5.0 (32 GT/s), 4.0 (16 GT/s), 3.1 (8 GT/s) and PIPE (32-bit) specifications
- Application interface choices for CXL.io include the Synopsys Native PCIe interface or optional Arm® AMBA® 4 AXI and AMBA 3 AXI interface support
- Choice of interfaces optimized for CXL.cache and CXL.mem - either the Synopsys Native CXL interface or the Arm AMBA CXS interface
- Based on silicon-proven 512-bit PCIe 6.0 controller design
- Standards-compliant Synopsys IDE Security Module protects data transfer for SoCs using the CXL 3.0 and 2.0 interface
|CXL 2.0 Premium Controller Device/Host/DM 512b||STARs
|CXL 2.0 Premium Controller Device/Host/DM 512b with AMBA bridge||STARs
|CXL 2.0 Premium Controller Device/Host/DM 512b with AMBA bridge + LTI and MSI-GIC interfaces||STARs
|Adds security Interfaces, features to CXL 2.0 Premium controllers||STARs