Synopsys IDE Security IP Modules for CXL 2.0/3.0

The Compute Express Link (CXL) interface protocol enables low-latency data communication between system-on-chip (SoC) and general-purpose accelerators, memory expanders, and smart I/O devices requiring high performance, heterogeneous computing for data-intensive workloads.

The Synopsys CXL 2.0/3.0 Integrity and Data Encryption (IDE) Security IP Modules provide confidentiality, integrity, and replay protection for FLITs in the case of CXL.cache and CXL.mem protocols and for Transaction Layer Packets (TLP)/FLITs in the case of The Security Modules are compliant with the IDE specification as defined for CXL protocols which also reference PCI Express IDE specifications for the protocol. The Synopsys CXL IDE Security Modules integrate seamlessly with the Synopsys CXL Controllers to accelerate SoC integration.

Synopsys CXL Controllers with IDE security IP module support TEE Device Interface Security Protocol (TDISP) for TDISP standardized framework defines how to secure the interconnect between virtual machine hosts and devices, regardless of where the data center resides or who has access to the servers inside. Synopsys CXL Controllers with IDE enable designers to build full TDISP support in their hyperscale SoCs and mitigate against data and system attacks, addressing the challenges of secure I/O virtualization.

The Synopsys CXL 2.0 IDE Security Module offers plug-and-play connectivity to the Synopsys CXL 2.0 Controller via TLP and FLIT packet-based interfaces, for .io and .cache/.mem respectively. The data interface matches the data width used by the controller, e.g. 512-bit. For the .io, the number of used TLP prefixes can also be configured to deploy an area-optimized cryptographic core.

Learn about the broad portfolio of Security Solutions for Interfaces.

Synopsys IDE Secure Module for CXL 2.0 Datasheet


Downloads and Documentation
  • Compliant with the CXL 2.0 IDE specifications for CXL.cache/mem
  • Compliant with PCI Express IDE specification for
  • High-performance AES-GCM based packet encryption, decryption, authentication
  • Support for TDISP
  • Seamless integration with Synopsys Controller IP
    • FLIT interfacing for CXL.cache/mem
    • TLP packet-based interfacing for
    • Sync/fail/status messaging
  • Supports CXL 2.0 data rates
  • Customer configurable
    • Aligns with Synopsys CXL 2.0/3.0 controller configuration options
    • Data bus width: 512
    • Lanes: x8, x16
    • Support for all protocols CXL.cache/mem/io or only CXL.cache/mem
  • CXL.cache/mem
  • Containment & skid modes
  • Early MAC termination
  • Optimized for area, performance & latency
  • Multi-stream support
  • PCRC calculation & validation
  • Efficient key control & refresh
  • Bypass mode
CXL 2.0 Integrity and Data Encryption Security ModuleSTARs Subscribe

Description: CXL 2.0 Integrity and Data Encryption Security Module
Name: dwc_cxl_2_ide_security_module
Version: 1.04a-lca05
ECCN: 5D002.b2/ENC
Product Type: DesignWare Cores
Download: dw_iip_DWC_cxl_ide
Product Code: F910-0