Synopsys IDE Security IP Modules for CXL 2.0/3.0

The Compute Express Link (CXL) interface protocol enables low-latency data communication between system-on-chip (SoC) and general-purpose accelerators, memory expanders, and smart I/O devices requiring high performance, heterogeneous computing for data-intensive workloads.

The Synopsys CXL 2.0/3.0 Integrity and Data Encryption (IDE) Security IP Modules provide confidentiality, integrity, and replay protection for FLITs in the case of CXL.cache and CXL.mem protocols and for Transaction Layer Packets (TLP)/FLITs in the case of CXL.io. The Security Modules are compliant with the IDE specification as defined for CXL protocols which also reference PCI Express IDE specifications for the CXL.io protocol. The Synopsys CXL IDE Security Modules integrate seamlessly with the Synopsys CXL Controllers to accelerate SoC integration.

The Synopsys CXL 2.0 IDE Security Module offers plug-and-play connectivity to the Synopsys CXL 2.0 Controller via TLP and FLIT packet-based interfaces, for .io and .cache/.mem respectively. The data interface matches the data width used by the controller, e.g. 512-bit. For the .io, the number of used TLP prefixes can also be configured to deploy an area-optimized cryptographic core.

DesignWare IDE Security IP Module for CXL 2.0