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The Synopsys CXL 2.0 Integrity and Data Encryption (IDE) Security IP Module provides confidentiality, integrity and replay protection for FLITs in the case of CXL.cache and CXL.mem protocols and for Transaction Layer Packets (TLP) in the case of CXL.io. The Security Module is compliant with the IDE specification as defined for CXL 2.0 which also references PCI Express IDE specification for the CXL.io protocol. The Synopsys CXL 2.0 IDE Security Module integrates seamlessly with the Synopsys CXL controllers to accelerate SoC integration.
The Synopsys CXL 2.0 IDE Security Module supports full-duplex for .cache/.mem and .io Rx and Tx directions. It provides efficient encryption/decryption and authentication of FLITs and TLPs, based on optimized low latency AES-GCM cryptographic cores, that are specially developed to meet an optimal area vs. performance implementation.
Learn about the broad portfolio of Security Solutions for Interfaces.
Highlights & Key Features
- Compliant with the CXL 2.0 IDE specifications for CXL.cache/mem
- Compliant with PCI Express IDE specification for CXL.io
- High-performance AES-GCM based packet encryption, decryption, authentication
- Seamless integration with Synopsys Controller IP
- FLIT interfacing for CXL.cache/mem
- TLP packet-based interfacing for CXL.io
- Sync/fail/status messaging
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