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IDE Security IP Module for CXL 2.0
The Compute Express Link (CXL) interface protocol enables low-latency data communication between system-on-chip (SoC) and general-purpose accelerators, memory expanders, and smart I/O devices requiting high performance, heterogeneous computing for data-intensive workloads.
The Synopsys DesignWare® CXL 2.0 Integrity and Data Encryption (IDE) Security IP Module provides confidentiality, integrity and replay protection for FLITs in the case of CXL.cache and CXL.mem protocols and for Transaction Layer Packets (TLP) in the case of CXL.io. The Security Module is compliant with the IDE specification as defined for CXL 2.0 which also references PCI Express IDE specification for the CXL.io protocol. The DesignWare CXL 2.0 IDE Security Module integrates seamlessly with the Synopsys DesignWare CXL controllers to accelerate SoC integration.
The DesignWare CXL 2.0 IDE Security Module offers plug-and-play connectivity to the DesignWare CXL 2.0 Controller via TLP and FLIT packet based interfaces, for .io and .cache/.mem respectively. The data interfaces matches the data width used by the controller, e.g. 512-bit. For the .io, the number of used TLP prefixes can also be configured to deploy an area-optimized cryptographic core.
DesignWare IDE Security IP Module for CXL 2.0
- Compliant with the CXL 2.0 IDE specifications for CXL.cache/mem
- Compliant with PCI Express IDE specification for CXL.io
- High-performance AES-GCM based packet encryption, decryption, authentication
- Seamless integration with Synopsys DesignWare controller IP
- FLIT interfacing for CXL.cache/mem
- TLP packet-based interfacing for CXL.io
- Sync/fail/status messaging
- Supports CXL 2.0 data rates
- Customer configurable
- Aligns with DesignWare CXL 2.0 controller configuration options
- Data bus width: 512
- Lanes: x8, x16
- Support for all protocols CXL.cache/mem/io or only CXL.cache/mem
- CXL.cache/mem
- Containment & skid modes
- Early MAC termination
- Optimized for area, performance & latency
- Multi-stream support
- PCRC calculation & validation
- Efficient key control & refresh
- Bypass mode
| Description: | CXL 2.0 Integrity and Data Encryption Security Module |
| Name: | dwc_cxl_2_ide_security_module |
| Version: | 1.00a-lca01 |
| Product Type: | DesignWare Cores |
| Documentation: | |
| Download: | dw_iip_DWC_cxl_ide |
| Product Code: | F910-0 |