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The Synopsys CXL 3.x Integrity and Data Encryption (IDE) Security IP Module provides confidentiality, integrity, and replay protection for flow control units (FLITs) in the case of CXL.cache and CXL.mem protocols, and for FLITs and Transaction Layer Packets (TLP) in the case of CXL.io.
The Security Module implements the IDE specification as defined for CXL 3.x which also references PCI Express 6.x IDE specification for the CXL.io protocol. The Synopsys CXL 3.x IDE Security Module integrates seamlessly with the Synopsys CXL controllers to accelerate SoC integration.
The Synopsys CXL 3.x IDE Security Module provides full-duplex .cache/.mem/.io support with efficient encryption/decryption and authentication of FLITs and TLPs, based on optimized low latency AES-GCM cryptographic cores, that are specially developed for optimal area, performance, and latency implementations.
Learn about the broad portfolio of Security Solutions for Interfaces.
Highlights & Key Features
- Support for PCIe 6.0/6.1/6.2 IDE specification for CXL.io
- Support for CXL 3.x IDE specification for CXL.cache/mem
- High-performance AES-GCM-based packet encryption, decryption, authentication
- FIPS 140-3 certification support
- TDISP support for CXL.io
- Seamless integration with Synopsys Controllers IP
- FLIT interfacing for CXL.cache/mem
- FLIT/TLP interfacing for CXL.io
- Efficient sync/fail/status messaging
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