DesignWare 112G Ethernet PHY IP

The DesignWare 112G Ethernet PHY IP, an integral part of Synopsys' high-speed SerDes IP portfolio, enables true long reach channels for up to 800G hyperscale data center, networking, and AI SoCs requiring high bandwidth and low latency. Using leading-edge design, analysis, simulation, and measurement techniques, the 112G Ethernet PHY delivers exceptional signal integrity and jitter performance that exceeds the IEEE 802.3ck and OIF standards electrical specifications. The PHY is small in area, high in performance demonstrating zero BER in greater than 40dB channels, and power-efficient at less than 5pJ/bit.

The 112G Ethernet PHY’s flexible layout maximizes bandwidth per die-edge by allowing placement of square macros in a multi-row structure and along all edges of the die. The PHY supports the Pulse-Amplitude Modulation 4-Level (PAM-4), Non- Return-to-Zero (NRZ) signaling, and independent, per lane data rates for ultimate flexibility to address broad range of protocols and applications. The configurable transmitter and DSP-based receiver with analog-to-digital converter (ADC) enable designers to control and optimize signal integrity and performance. The CCA algorithms provide robust performance across voltage and temperature variations. The low jitter PLLs, clock, and data recovery circuits provide robust timing recovery and better jitter performance, while the embedded bit error rate (BER) tester and non-destructive 2D eye monitor capability provide on-chip testability and visibility into channel performance.

Combined with Synopsys' routing feasibility study, packages substrate guidelines, signal and power integrity models, and thorough crosstalk analysis, Synopsys provides a comprehensive 112G Ethernet PHY solution for fast and reliable SoC integration.

Additional Resources
Webinar: Keeping Latency to a Minimum with 400G/800G Ethernet IP
Article: Anatomy of an Integrated Ethernet PHY IP for High Performance Computing SoCs
Article: Tightly-Coupled Analog and DSP Architecture for Best 112G SerDes IP Performance
News: Synopsys Demonstrates Silicon Proof of DesignWare 112G Ethernet PHY IP in 5nm Process for High-Performance Computing SoCs
Web page: DesignWare High-Speed SerDes PHY IP solutions

DesignWare 112G Ethernet PHY IP Datasheet