Synopsys ARC MetaWare MX Development Toolkit

The Synopsys ARC® MetaWare MX Development Toolkit is a complete suite of tools, SDKs, runtime software and libraries that provide everything needed to program the ARC NPX NPU (neural processing unit) IP and ARC VPX DSP IP. The product provides a modular solution to accelerate embedded, DSP, machine learning and vision applications.


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The following table shows the main components of the MetaWare MX Development Toolkit:

Component Description
MetaWare Development Toolkit The MetaWare Development Toolkit contains the C/C++, OpenCL C, and Vector C compilers that support programming for kernel and application development. It also includes a debugger and ARC nSIM, which is an instruction set simulator for debugging, profiling, and optimizing kernels and applications
Simulink® Model-Based Design Support Automatically generates optimized code from a MATLAB® model to execute on the ARC Processr
MetaWare Compute Libraries These are libraries optimized for execution on ARC processors and include Vector DSP, a Vector Linear Algebra Library and a Vision Library
MetaWare Neural Network SDK The SDK includes a neural network compiler that compiles and runs AI models optimized for the ARC NPX NPU IP and ARC VPX processors
Virtual Platforms Includes simulation models for virtual platforms that enable system-level model integration for architectural exploration and early software development prior to silicon

MetaWare Development Toolkit

The MetaWare Development Toolkit contains compilers, a debugger and a simulator. It includes the MetaWare C/C++ Compiler and MetaWare OpenCL C Compiler used to build applications and kernels to execute on ARC processors. The compilers support manual and automatic vectorization and provide methods for additional optimizations through software pipelining and control of instruction scheduling. The MetaWare Debugger is used to debug, profile, and optimize applications and kernels built with these compilers. ARC nSIM is an Instruction Set Simulator with a Near Cycle Approximate Mode (NCAM) used for early software development such as algorithm development.

Simulink Model-Based Design Support

Model-based Design takes advantage of ARC processor Hardware Support Packages. It allows users to develop algorithm at a higher level of abstraction. The Simulink® Model-Based Design flow automatically generates Vector DSP Library C code with highly-optimized library function calls to the ARC processor. The Vector DSP Library and Vector Linear Algebra Library are used as code replacement libraries to produce the optimized code that can then be compiled and run on the ARC processor.

DSP, Linear Algebra and Vision Libraries

The MetaWare Vector DSP library is a software library that provides a set of optimized software DSP functions that can ease the development of applications for the Vector DSP of the ARC VPX processor. By using the library, you can simplify your application development by applying pre-verified functions that have been optimized for the ARC VPX processors.

The MetaWare Vector Linear Algebra Library is a software library of BLAS/LAPACK and supplementary algorithms. It is available in an OpenCL C and a C/C++ version. This library can be used to easily develop applications requiring linear algebra functionality.

These libraries can be used by the Simulink Model-Based Design Flow for code replacement to produce highly optimized code for the ARC VPX processors.

The Vision library provides a library of classic computer vision kernels to accelerate vision algorithms and applications running on the Synopsys ARC VPX Processor. Kernels include resize, color space conversion, various filters and pixel-wise processing. Kernels can be used standalone or in conjunction with the NN SDK to do pre- and post-processing of neural network data.

MetaWare NN SDK

The MetaWare NN SDK provides a Neural Network Compiler and runtime software to execute a neural network model on the ARC NPX NPU IP or ARC VPX DSPs. The MetaWare NN Compiler takes a pre-trained model, implemented in the TensorFlow framework or available in the ONNX format, and compiles it to run on the ARC NPX NPU IP or ARC VPX DSPs. It can also produce a standalone fixed-point model to aid in comparing the accuracy when moving from floating point to fixed point.

Virtual Platform Simulation Models

The MetaWare Toolkit contains Simulation models for the relevant ARC IP to enable system-level simulation for early software development, benchmarking, and architectural exploration before hardware availability. This includes functional and cycle-based models of ARC NPX NPU IP and ARC VPX DSPs and ARC/ARC-V processors, as well as SystemC support and integration layer for the Synopsys Virtualizer and Platform Architect SoC Virtual Prototyping solutions.


Synopsys ARC MetaWare MX Development Toolkit Datasheet

 

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MetaWare MX Development ToolkitSTARs Subscribe

Description: MetaWare MX Development Toolkit
Name: dw_arc_metaware_mx
Version: 1.2_SP1
ECCN: EAR99/NLR
STARs: Open and/or Closed STARs
myDesignWare: Subscribe for Notifications
Product Type: DesignWare Cores
Documentation:
Download: arc_MWDT_MX
Product Code: H274-0