Virtual Prototyping
Accelerate pre-RTL embedded software development, hardware/software integration, and system validation
Architecture Design
Quickly explore tradeoffs in your SoC architecture to achieve optimal product performance and cost to avoid over- or under-design
FPGA-Based Prototyping
Accelerate the creation of your ASIC prototype with a high-speed hardware prototyping environment including a comprehensive software flow
Core Optimization
Differentiate your product with the right combination of performance, power and area for your most design-critical cores
Design Flow Deployment
Optimize your design flow to address the latest design challenges
Physical Design Assistance
Leverage our tape-out proven flows and project experience to implement your very-deep submicron chip
IP Integration & SoC Verification
Get to market faster and reduce SoC design and verification cost by applying best practices in RTL creation and functional verification
Submitting this form will give you access to a virtual machine containing a DesignWare® ARC® 600 processor for a period of 24 hours. You will be able to experiment with processor options in the ARChitect processor configurator, run sample code in simulation and observe performance & area trade-offs of standard and custom extensions.
Please print and read the Terms and Conditions of the Synopsys DesignWare ARC 600 cloud demonstration site, featuring the ARChitect processor configurator, MetaWare Development Toolkit and ARC 600 IP libraries.
Complete the following form, then click the "continue >>" button below.
