With the tremendous data and bandwidth growth in our connected world, security is essential to protect private and sensitive data as it moves across systems to storage, including memory. While the volume and variety of data are growing, so is the need for higher capacity, faster access, and accelerated processing. Designers are turning to high-performance, low-latency memory encryption solutions to preserve performance while protecting data over the latest generations of DDR, LPDDR, GDDR, and HBM memory interfaces.
AES-XTS, or as it is sometimes referred XTS-AES, is the de-facto cryptographic algorithm for protecting the confidentiality of data-at-rest on storage devices. It is a standards-based symmetric algorithm defined by NIST SP800-38E and IEEE Std 1619-2018 specifications. It allows for pipelined architectures that can scale in performance to Terabits per second (Tbps) bandwidth.
Synopsys offers two high performance configurable AES-XTS IP cores to give customers options to configure and tune the optimal solution for their application. The core with the highest performance is the Synopsys Ultra High-Performance AES-XTS/ECB Cryptographic IP core with support from 128 bits/cycle to 4096 bits/cycle throughput, in 128 bits/cycle increments throughput (e.g. 4Tbps @ 1GHz; scales linearly with the maximum frequency achievable in a particular process).
The Synopsys Ultra High-Performance AES XTS/ECB IP is based on a pipelined architecture that allows the performance to scale efficiently to Tbps throughput for various data traffic patterns, while keeping the latency and area as low as possible even for multiple cryptographic contexts in flight, and to achieve high operating frequencies in advanced process nodes.
Synopsys Ultra High-Performance AES-XTS/ECB Cryptographic Cores are standards-compliant, support encryption and decryption for all key sizes, allow for seamless context switching for a high number of contexts, support efficient keys setup/refresh, are FIPS 140-3 certification ready and passed NIST CAVP validation.
In addition, the Synopsys Ultra-High Performance AES-GCM/CTR Cryptographic Cores are FIPS 140-3 certification ready and passed NIST CAVP validation.
Synopsys Ultra High-Performance AES-XTS/ECB IP Core Datasheet
|Description:||High Performance AES-XTS/ECB Core|
|Product Type:||DesignWare Cores|
|Documentation:||Contact Us for More Information|
|Product Code:||H181-0, H594-0|