Synopsys General-Purpose IO (GPIO) Library IP delivers the input/output (IO) functionality and reliability required for system-on-chip (SoC) designs across mobile, automotive, and high-performance computing (HPC) applications. Silicon-proven and available in multiple foundries and process technologies ranging from 3nm to 22nm, Synopsys GPIO IP ensures broad compatibility and robust performance.

Designed to support multiple voltage levels, the Synopsys GPIO library provides a comprehensive set of support cells—including supply cells, corner spacers, diode breakers, and terminators—enabling the creation of complete IO pad rings for SoCs. The library is fully compatible with flip-chip packaging, offering flexibility for advanced assembly methods. Each GPIO driver pad integrates essential features such as Schmitt-Trigger functionality, programmable drive strength, and pull-up/pull-down resistors, all with robust HBM and CDM electrostatic discharge (ESD) protection.

The Synopsys GPIO IP portfolio empowers designers to meet critical power, performance, and area (PPA) objectives, delivering reliable, low-risk solutions and accelerating time-to-market.

Additionally, the library includes High-Speed Test IO, a breakthrough solution that enables test engineers and chiplet designers to perform high-speed, efficient testing of advanced semiconductor designs while reducing hardware complexity and costs.

Highlights & Datasheets

  • Supports 1.8V/2.5V/3.3V mixed-voltage-tolerant/failsafe output buffer
  • Fully programmable output driver strengths, input Schmitt trigger, and output slew rate
  • Supports circuit-under-pad (CUP), non-CUP-inline and staggered-bond pad placement
  • Supports retention and bus-keeper feature
  • Operating speed in excess of 250MHz
  • Robust ESD (up to 7A CDM, 2KV HBM) and latch-up protection circuitry
  • Automotive G1/G2 supported, ASIL-B certified
  • Silicon-validated IP
  • Available in multiple foundries and a wide range of technology nodes

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