The DesignWare USB-C 3.1/DisplayPort Tx 1.3 Tx IP solution consists of USB-C 3.1/DisplayPort 1.3 PHYs, USB-C 3.1/DisplayPort 1.3 controllers (Device, Host, or Dual-Role Device) with HDCP 2.2 content protection, verification IP, IP subsystems, IP prototyping kits and IP software development kits (SDKs). These elements accelerate development of advanced chip designs delivering video, data and power over a single Type-C connector.

The DesignWare USB-C 3.1/DisplayPort Tx 1.3 Tx IP is targeted for integration into SoCs that support connections to high-definition (HD), 2K, 4K, and 8K Ultra High Definition (UHD) display from mobile devices, set-top boxes and other applications requiring fast data transfer and output of high-resolution content. The DesignWare IP solution delivers up to 10 Gbps data rates and simplifies users’ USB connection with reversible plug orientation and cable direction, bi-directional power and the DisplayPort alternate mode. The DisplayPort 1.3 alternate mode uses existing SuperSpeed USB lanes over USB Type-C connectors and cables to deliver up to 32.4 Gbps maximum link bandwidth with each of the four lanes running at 8.1 Gbps. The DesignWare IP USB-C 3.1/DisplayPort 1.3 Tx IP solution simplifies integration and reduces system-level costs by removing requirements for external crossbar switch components for the USB and DisplayPort datapaths.

The DesignWare USB-C 3.1/DisplayPort 1.3 Tx IP solution integrates HDCP 2.2 content security, which is required to play back UHD 4K and higher-resolution content over DisplayPort 1.3 alternate mode. It creates a secure connection between a source and display by using industry standard public key and advanced encryption algorithms for successful content transfer. Synopsys’ HDCP 2.2 content protection IP provides designers with a complete and highly secure implementation of the HDCP 2.2 standard, including the entire control plane processing with authentication and key exchange protocols, as well as key stream generation. Incorporating HDCP 2.2 content protection in the DesignWare USB-C 3.1/DisplayPort 1.3 Tx IP solution helps designers meet the stringent compliance requirements of the DCP LLC licensing authority.

As the leading supplier of USB IP, Synopsys enables designers to accelerate the integration of high-performance USB Type-C connectivity into their SoCs, while enabling secure delivery of high-definition video content.

DesignWare SuperSpeed USB 3.1 IP Solution

Highlights

Features

Products

Downloads and Documentation

Industry’s only USB Type-C IP solution consisting of USB-C 3.1/DisplayPort 1.3 Tx PHYs, USB-C 3.1/DisplayPort 1.3 Tx controllers with HDCP 2.2 and HDCP 1.4 content protection, verification IP, IP subsystems, IP prototyping kits, and IP software development kits
Solution supports USB Type-C, SuperSpeed USB 3.1 at 10 Gbps, SuperSpeed USB 3.0 at 5 Gbps and High-Speed USB (USB 2.0) as well as DisplayPort 1.3 Tx supporting RBR, HBR1, HBR2 and HBR3 bitrates
Controllers support Device, Host, and Dual-Role Device USB-C 3.1 as well as DisplayPort 1.3 Tx with HDCP 2.2 content protection
DesignWare USB-C 3.1/DisplayPort 1.3 Tx PHY optimized for USB Type-C connectivity, conforming to latest USB 3.1 and DisplayPort 1.3 specifications
Supports Type-C Port Controller, Type-C Port Controller Interface and Type-C Port Manager specifications for flexible hardware and software partitioning

USB-C 3.1/DisplayPort 1.3 Tx Controller IP

Lowest risk: Based on proven USB 3.0 controller shipped in 100s of millions of units
Lowest power: Extend battery life in mobile devices (USB power saving modes, Uniform Power Format, hibernation option with dual power rails)
Configurable data buffering options to optimize performance vs area
Supports all USB speed modes
DisplayPort 1.3a Transmit features optimized for USB Type-C
Integrates with DesignWare HDCP 2.2 Embedded Security Modules

USB-C 3.1/DisplayPort 1.3 Tx PHY IP

Supports 10 Gbps and 5 Gbps data rates
Supports RBR, HBR1, HBR2 and HBR3 data rates
Low active and standby power
Small area for low silicon cost
Optimized USB Type-C connectivity support

DisplayPort Transmit Controller ASIL Compliant	STARs	Subscribe
DisplayPort Transmit Controller	STARs	Subscribe
USB 3.1 DisplayPort PHY - TSMC 10FF, North/South Poly Orientation	STARs	Subscribe
USB-C 3.1/DP TX PHY for SS SF5A , North/South Poly Orientation	STARs	Subscribe
USB-C 3.1/DP TX PHY for GF 22FD-SOI, North/South Poly Orientation	STARs	Subscribe
USB-C 3.1/DP TX PHY for Samsung 11LPP, North/South Poly Orientation	STARs	Subscribe
USB-C 3.1/DP TX PHY for Samsung 14LPP, North/South Poly Orientation	STARs	Subscribe
USB-C 3.1/DP TX PHY for SS SF5A, North/South Poly Orientation	STARs	Subscribe
USB-C 3.1/DP TX PHY for TSMC 12FFC, North/South Poly Orientation	STARs	Subscribe
USB-C 3.1/DP TX PHY for TSMC 16FFC, North/South Poly Orientation	STARs	Subscribe
USB-C 3.1/DP TX PHY for TSMC 6FF, North/South Poly Orientation	STARs	Subscribe
USB-C 3.1/DP TX PHY for TSMC 7FF, North/South Poly Orientation	STARs	Subscribe
USB-C 3.1 DP/TX PHY ebdaux for TSMC N5, North/South poly orientation	STARs	Subscribe
SuperSpeed USB 3.1 Device Controller	STARs	Subscribe
SuperSpeed USB 3.1 DRD Controller	STARs	Subscribe
SuperSpeed USB 3.1 Host Controller	STARs	Subscribe

Description:	DisplayPort Transmit Controller
Name:	dwc_dptx
Version:	3.00a
ECCN:	3E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes Synopsys Controller IP DisplayPort Transmit Controller AppNote (Document Version 1.10) ( PDF \| HTML ) Databooks DesignWare Cores DisplayPort Transmit Controller Databook (3.00a) ( PDF \| HTML ) DesignWare Cores DisplayPort Transmit Controller Databook with Changebar (3.00a) ( PDF ) Installation Guide DesignWare Cores DisplayPort Transmit Controller Install Guide (3.00a) ( PDF ) Release Notes DesignWare Cores DisplayPort Transmit Controller Release Notes (3.00a) ( PDF ) User Guides DesignWare Cores DisplayPort Transmit Controller User Guide (3.00a) ( PDF \| HTML ) DesignWare Cores DisplayPort Transmit Controller User Guide with Changebar (3.00a) ( PDF )
Toolsets:	Qualified Toolsets
Download:	dw_iip_DWC_dptx
Product Code:	G259-0, G260-0, I250-0

Description:	DisplayPort Transmit Controller ASIL Compliant
Name:	dwc_ac_dptx
ECCN:	3E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Contact Us for More Information

Description:	SuperSpeed USB 3.1 Device Controller
Name:	dwc_usb_3_1_device
Version:	2.10a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare Cores USB3.1 SSP PHY and Controller Integration Guide (App Note Version 1.00a) ( PDF \| HTML ) Designware Cores Enhanced SuperSpeed USB 3.1 Controller Packaged Verification Environment Application Note (App Note Version 1.00a) ( PDF \| HTML ) Designware Cores Enhanced SuperSpeed USB 3.1 Controller Simulation Debug Guide (App Note Version 1.00a) ( PDF \| HTML ) Databooks Designware Cores Enhanced SuperSpeed USB 3.1 Controller Databook (2.10a) ( PDF \| HTML ) Designware Cores Enhanced SuperSpeed USB 3.1 Controller Databook - with Change Bars (2.10a) ( PDF ) Datasheets DesignWare SuperSpeed USB 3.1 IP Solution ( PDF ) Synopsys USB-C 3.1/DisplayPort 1.4 TX IP Complete Solution ( PDF ) Installation Guide Designware Cores Enhanced SuperSpeed USB 3.1 Controller Installation Guide (2.10a) ( PDF \| HTML ) Programming Guides Designware Cores Enhanced SuperSpeed USB 3.1 Controller Programming Guide (2.10a) ( PDF \| HTML ) Designware Cores Enhanced SuperSpeed USB 3.1 Controller Programming Guide - with Change Bars (2.10a) ( PDF ) Release Notes Designware Cores Enhanced SuperSpeed USB 3.1 Controller Release Notes (2.10a) ( PDF ) Training Videos Configuring DWC_usb3 Controller as a Device ( HTML ) DWC_usb3 Controller Clocks and Clock Synthesis ( HTML ) Managing Power in DWC_usb3 ( HTML ) User Guides Designware Cores Enhanced SuperSpeed USB 3.1 Controller User Guide (2.10a) ( PDF \| HTML ) Designware Cores Enhanced SuperSpeed USB 3.1 Controller User Guide - with Change Bars (2.10a) ( PDF ) White Papers Addressing Three Critical Challenges of USB Type-C Implementation ( PDF ) USB 3.2: A USB Type-C Challenge for SoC Designers ( PDF ) USB 3.2: The Latest USB Type-C Challenge for SoC Designers ( PDF )
Toolsets:	Qualified Toolsets
Download:	dw_iip_DWC_usb31
Product Code:	A868-0

Description:	SuperSpeed USB 3.1 DRD Controller
Name:	dwc_usb_3_1_drd
Version:	2.10a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare Cores USB3.1 SSP PHY and Controller Integration Guide (App Note Version 1.00a) ( PDF \| HTML ) Designware Cores Enhanced SuperSpeed USB 3.1 Controller Packaged Verification Environment Application Note (App Note Version 1.00a) ( PDF \| HTML ) Designware Cores Enhanced SuperSpeed USB 3.1 Controller Simulation Debug Guide (App Note Version 1.00a) ( PDF \| HTML ) Databooks Designware Cores Enhanced SuperSpeed USB 3.1 Controller Databook (2.10a) ( PDF \| HTML ) Designware Cores Enhanced SuperSpeed USB 3.1 Controller Databook - with Change Bars (2.10a) ( PDF ) Datasheets DesignWare SuperSpeed USB 3.1 IP Solution ( PDF ) Synopsys USB-C 3.1/DisplayPort 1.4 TX IP Complete Solution ( PDF ) Installation Guide Designware Cores Enhanced SuperSpeed USB 3.1 Controller Installation Guide (2.10a) ( PDF \| HTML ) Programming Guides Designware Cores Enhanced SuperSpeed USB 3.1 Controller Programming Guide (2.10a) ( PDF \| HTML ) Designware Cores Enhanced SuperSpeed USB 3.1 Controller Programming Guide - with Change Bars (2.10a) ( PDF ) Release Notes Designware Cores Enhanced SuperSpeed USB 3.1 Controller Release Notes (2.10a) ( PDF ) Training Videos Configuring DWC_usb3 Controller as a Device ( HTML ) Configuring DWC_usb3 Controller as a Host ( HTML ) DWC_usb3 Controller Clocks and Clock Synthesis ( HTML ) Managing Power in DWC_usb3 ( HTML ) User Guides Designware Cores Enhanced SuperSpeed USB 3.1 Controller User Guide (2.10a) ( PDF \| HTML ) Designware Cores Enhanced SuperSpeed USB 3.1 Controller User Guide - with Change Bars (2.10a) ( PDF ) White Papers Addressing Three Critical Challenges of USB Type-C Implementation ( PDF ) USB 3.2: A USB Type-C Challenge for SoC Designers ( PDF ) USB 3.2: The Latest USB Type-C Challenge for SoC Designers ( PDF )
Toolsets:	Qualified Toolsets
Download:	dw_iip_DWC_usb31
Product Code:	A871-0

Description:	SuperSpeed USB 3.1 Host Controller
Name:	dwc_usb_3_1_host
Version:	2.10a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare Cores USB3.1 SSP PHY and Controller Integration Guide (App Note Version 1.00a) ( PDF \| HTML ) Designware Cores Enhanced SuperSpeed USB 3.1 Controller Packaged Verification Environment Application Note (App Note Version 1.00a) ( PDF \| HTML ) Designware Cores Enhanced SuperSpeed USB 3.1 Controller Simulation Debug Guide (App Note Version 1.00a) ( PDF \| HTML ) Databooks Designware Cores Enhanced SuperSpeed USB 3.1 Controller Databook (2.10a) ( PDF \| HTML ) Designware Cores Enhanced SuperSpeed USB 3.1 Controller Databook - with Change Bars (2.10a) ( PDF ) Datasheet DesignWare SuperSpeed USB 3.1 IP Solution ( PDF ) Installation Guide Designware Cores Enhanced SuperSpeed USB 3.1 Controller Installation Guide (2.10a) ( PDF \| HTML ) Programming Guides Designware Cores Enhanced SuperSpeed USB 3.1 Controller Programming Guide (2.10a) ( PDF \| HTML ) Designware Cores Enhanced SuperSpeed USB 3.1 Controller Programming Guide - with Change Bars (2.10a) ( PDF ) Release Notes Designware Cores Enhanced SuperSpeed USB 3.1 Controller Release Notes (2.10a) ( PDF ) Training Videos Configuring DWC_usb3 Controller as a Host ( HTML ) DWC_usb3 Controller Clocks and Clock Synthesis ( HTML ) Managing Power in DWC_usb3 ( HTML ) User Guides Designware Cores Enhanced SuperSpeed USB 3.1 Controller User Guide (2.10a) ( PDF \| HTML ) Designware Cores Enhanced SuperSpeed USB 3.1 Controller User Guide - with Change Bars (2.10a) ( PDF ) White Papers USB 3.2: A USB Type-C Challenge for SoC Designers ( PDF ) USB 3.2: The Latest USB Type-C Challenge for SoC Designers ( PDF )
Toolsets:	Qualified Toolsets
Download:	dw_iip_DWC_usb31
Product Code:	A869-0, A870-0, A872-0

Description:	USB 3.1 DisplayPort PHY - TSMC 10FF, North/South Poly Orientation
Name:	dwc_usb31dpphy_tsmc10ffx4ns
Version:	1.03a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes Consumer 10 USB 3.1 DP PHY ATE Test Bench Application Note for TSMC10FF ( PDF ) DP AUX/AUX-I2C PHY INTEGRATION REVIEW CHECKLIST for TSMC10FF (1.0) ( PDF ) USB 3.1/DP Alt PHY Integration Review Checklist for TSMC10FF ( PDF ) Databooks DP AUX PHY for TSMC 10 FF Databook ( PDF ) USB 3.1/DP Alt PHY for TSMC 10 FF Databook ( PDF ) White Papers USB 3.2: A USB Type-C Challenge for SoC Designers ( PDF ) USB 3.2: The Latest USB Type-C Challenge for SoC Designers ( PDF )
Download:	USBC3.1-DP-TX-PHY_CUHSN-TS_10FF
Product Code:	C010-0

Description:	USB-C 3.1 DP/TX PHY ebdaux for TSMC N5, North/South poly orientation
Name:	dwc_usbc31dptx_ebdaux_phy_tsmc5ffns
Version:	4.01c
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare Cores Type-C USB 3.1 DP PHY ATE Test Bench (Doc Version: 1.71a) ( PDF \| HTML ) SerDes PCB and Packaging Design Guide (Doc Version: 2.60a) ( PDF \| HTML ) Synopsys PHY IP Compilation Using the LC and FC End-User Platform (Doc Version: 1.11a) ( HTML ) Synopsys PHY IP Consumer 10G Compilation Using the LC and FC End-User Platform (Doc Version: 1.11a) ( PDF ) Synopsys PHY IP High Speed SerDes Gate-Level Simulations (Doc Version: 1.12a) ( PDF \| HTML ) Databooks DesignWare Cores Type-C USB3.1 SSP+ / DP Alt PHY for TSMC5FF (PHY Version: 4.01c) ( PDF \| HTML ) Type-C USB3.1SSP+ / DP Alt PCS for the DesignWare Cores Type-C USB3.1SSP+ / DP Alt PHY (PCS Version: 3.54b ( PDF \| HTML ) Reference Manual DesignWare Cores Type-C USB3.1 SSP+ / DP Alt PHY for TSMC5FF Reference Manual (PHY Version: 4.01c) ( PDF \| HTML ) Release Notes USBC3.1 / DP PHY x4 NS for TSMC5FF 1.2V Release Notes (PHY Version: 4.01c) ( TEXT )
Download:	dwc_usbc31dptx_ebdaux_phy_tsmc5ffns
Product Code:	E743-0

Description:	USB-C 3.1/DP TX PHY for GF 22FD-SOI, North/South Poly Orientation
Name:	dwc_usbc31dptxphy_gf22fdsoins
Version:	2.02a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes SerDes PCB and Packaging Design Guide (Doc Version: 2.60a) ( PDF \| HTML ) Synopsys PHY IP High Speed SerDes Gate-Level Simulations (Doc Version: 1.12a) ( PDF \| HTML ) Databooks DesignWare Cores Type-C DP AUX PHY for GF22FDSOI 1.8V (PHY Version: 2.02a) ( PDF \| HTML ) DesignWare Cores USB3.1SSP+ DP Alt PHY for GF22 FDSOI (PHY Version: 2.02a) ( PDF \| HTML ) Type-C - USB3.1SSP+ / DP Alt PCS for the DesignWare Cores Type-C - USB3.1SSP+ / DP Alt PHY for GF22FDSOI ( PDF \| HTML ) Release Notes DesignWare Cores USB3.1 TYPE-C/DP for GF22FDSOI 1.8V Release Notes (PHY Version: 2.02a) ( TEXT )
Download:	dwc_usbc31dptxphy_gf22fdsoins
Product Code:	E799-0

Description:	USB-C 3.1/DP TX PHY for Samsung 11LPP, North/South Poly Orientation
Name:	dwc_usbc31dptxphy_ss11lppns
Version:	1.03b
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare Cores Type-C USB 3.1 SS+ / DP Alt PHY ATE Test Bench for SS11LPP (PHY Version: 1.03b) ( PDF ) SerDes PCB and Packaging Design Guide (Doc Version: 2.60a) ( PDF \| HTML ) Synopsys PHY IP High Speed SerDes Gate-Level Simulations (Doc Version: 1.12a) ( PDF \| HTML ) Databooks DesignWare Cores Type-C USB 3.1 SS+ / DP Alt PHY for SS 11LPP (PHY Version: 1.03b) ( PDF \| HTML ) Type-C USB3.1SSP+ / DP Alt PCS for the DesignWare Cores Type-C USB3.1SSP+ / DP Alt PHY for SS11LPP (1.03b) ( PDF \| HTML ) Release Notes Type-C USB 3.1 / DP PHY X4 NS for SS 11LPP 1.8V Release Notes (PHY Version: 1.03b) ( TEXT )
Download:	dwc_usbc31dptxphy_ss11lppns
Product Code:	D834-0

Description:	USB-C 3.1/DP TX PHY for Samsung 14LPP, North/South Poly Orientation
Name:	dwc_usbc31dptxphy_ss14lppx4ns
Version:	1.04c
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare Cores Consumer 10 Type-C USB 3.1 SS+ / DP Alt PHY ATE Test Bench (Doc version: 1.31) ( PDF \| HTML ) SerDes PCB and Packaging Design Guide (Doc Version: 2.60a) ( PDF \| HTML ) Synopsys PHY IP High Speed SerDes Gate-Level Simulations (Doc Version: 1.12a) ( PDF \| HTML ) Databooks DesignWare Cores DP AUX PHY for SS14LPP 1.8 V ( PDF \| HTML ) DesignWare Cores Type-C USB 3.1 SSP+ / DP Alt PHY for SS14LPP (PHY Version: 1.04c) ( PDF \| HTML ) Type-C USB3.1SSP+ / DP Alt PCS for the DesignWare Type-C USB3.1SSP+ / DP Alt PHY for SS14LPP (1.04c) ( PDF \| HTML ) Release Notes Type-C USB 3.1 DPPHY x4 NS for SS14LPP 1.8V Release Notes (PHY Version: 1.04c) ( TEXT )
Download:	dwc_usbc31dptxphy_ss14lppx4ns
Product Code:	E042-0

Description:	USB-C 3.1/DP TX PHY for SS SF5A , North/South Poly Orientation
Name:	dwc_usbc31dptxphy_a00_ss5lpens
Version:	2.07a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare Cores Consumer 10G Type-C USB 3.1 DP PHY ATE Test Bench (Doc Version: 1.80a) ( PDF \| HTML ) Synopsys PHY IP High Speed SerDes Gate-Level Simulations (Doc Version: 1.12a) ( PDF \| HTML ) Databooks DesignWare Cores DP AUX PHY for SS5LPE 1.8 V (PHY Version: 2.07a) ( HTML ) DesignWare Cores DP AUX PHY for SS5LPE 1.8 V (PHY Version: 2.07a) ( PDF ) DesignWare Cores Type-C USB 3.1 SS+ DP Alt PHY A00 for SS5LPE PHY Databook (PHY Version: 2.07a) ( PDF \| HTML ) Type-C USB3.1SSP+ / DP Alt PCS for the DesignWare Cores Type-C USB3.1SSP+ / DP Alt PHY (PCS Version: 3.34b) ( PDF \| HTML ) Reference Manual DesignWare Cores Type-C USB 3.1 SS+ DP Alt PHY A00 for SS5LPE Reference Manual (PHY Version: 2.07a) ( PDF \| HTML ) Release Notes Type C USB3.1 DPPHY x4 NS PHY for SS 5LPE 1.8V A00 Release Notes (PHY Version: 2.07a) ( TEXT )
Download:	dwc_usbc31dptxphy_a00_ss5lpens
Product Code:	H864-0

Description:	USB-C 3.1/DP TX PHY for SS SF5A, North/South Poly Orientation
Name:	dwc_usbc31dptxphy_ss5lpens
Version:	2.03e
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare Cores Type-C USB 3.1 SS+ / DP Alt PHY ATE Test Bench for SS5LPE (Doc Version: 1.52a) ( PDF \| HTML ) SerDes PCB and Packaging Design Guide (Doc Version: 2.60a) ( PDF \| HTML ) Synopsys PHY IP High Speed SerDes Gate-Level Simulations (Doc Version: 1.12a) ( PDF \| HTML ) Databooks DesignWare Cores DP AUX PHY for SS5LPE 1.8 V (PHY Version: 2.03e) ( PDF \| HTML ) DesignWare Cores Type-C USB 3.1 SS+ DP Alt PHY for SS5LPE (PHY Version: 2.03e) ( PDF \| HTML ) Type-C - USB3.1SSP+ / DP Alt PCS for the DesignWare Cores Type-C USB3.1SSP+ / DP Alt PHY for SS5LPE (PHY Version: 2.03c) ( PDF \| HTML ) Release Notes Type-C USB 3.1 DP PHY X4 NS for SS5LPE 1.8V Release Notes (PHY Version: 2.03e) ( TEXT )
Download:	dwc_usbc31dptxphy_ss5lpens
Product Code:	F889-0

Description:	USB-C 3.1/DP TX PHY for TSMC 12FFC, North/South Poly Orientation
Name:	dwc_usbc31dptxphy_tsmc12ffcns
Version:	1.07a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare Cores Consumer Type-C USB3.1SS+/DP Alt PHY ATE Test Bench (Version: 1.50a) ( PDF \| HTML ) SerDes PCB and Packaging Design Guide (Doc Version: 2.60a) ( PDF \| HTML ) Synopsys PHY IP High Speed SerDes Gate-Level Simulations (Doc Version: 1.12a) ( PDF \| HTML ) Databooks DesignWare Cores DP AUX PHY for TSMC 12FFC (PHY Version: 1.07a) ( PDF \| HTML ) Synopsys PHY IP Type-C USB 3.1 SS+ / DP Alt PHY for TSMC 12FFC (PHY Version: 1.07a_d2) ( PDF \| HTML ) Type-C - USB3.1SSP+ / DP Alt PCS for the DesignWare Cores Type-C - USB3.1SSP+ / DP Alt PHY for TSMC12FFC (1.07a) ( PDF \| HTML ) Release Notes Type-C USB 3.1 DP PHY x4 NS for TSMC 12FFC 1.8V Release Notes (1.07a) ( TEXT ) White Papers USB 3.2: A USB Type-C Challenge for SoC Designers ( PDF ) USB 3.2: The Latest USB Type-C Challenge for SoC Designers ( PDF )
Download:	dwc_usbc31dptxphy_tsmc12ffcns
Product Code:	C455-0

Description:	USB-C 3.1/DP TX PHY for TSMC 16FFC, North/South Poly Orientation
Name:	dwc_usbc31dptxphy_tsmc16ffcx4ns
Version:	1.10a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DP AUX/AUX-I2C PHY INTEGRATION REVIEW CHECKLIST for TSMC16FFC (1.0) ( PDF ) DesignWare Cores Consumer Type-C USB3.1SS+/DP Alt PHY ATE Test Bench (Version: 1.50a) ( PDF \| HTML ) SerDes PCB and Packaging Design Guide (Doc Version: 2.60a) ( PDF \| HTML ) Synopsys PHY IP High Speed SerDes Gate-Level Simulations (Doc Version: 1.12a) ( PDF \| HTML ) USB 3.1/DP Alt PHY Integration Review Checklist for TSMC16 FFC ( PDF ) Databooks DesignWare Cores DP AUX PHY for TSMC16FFC (PHY Version: 1.10a) ( PDF \| HTML ) DesignWare Cores Type-C USB 3.1 SS+ / DP Alt PHY X4 for TSMC 16FFC (PHY Version: 1.10a_d1) ( PDF \| HTML ) USBC 3.1 SS+ PCS for the DesignWare Cores USBC 3.1 SS+ PHY (3.52a) ( PDF \| HTML ) Release Notes Type-C USB3.1 SS+ / DP Alt PHY x4 for TSMC 16FFC Release Notes (PHY Version: 1.10a) ( TEXT ) White Papers USB 3.2: A USB Type-C Challenge for SoC Designers ( PDF ) USB 3.2: The Latest USB Type-C Challenge for SoC Designers ( PDF )
Download:	dwc_usbc31dptxphy_tsmc16ffcx4ns
Product Code:	C009-0

Description:	USB-C 3.1/DP TX PHY for TSMC 6FF, North/South Poly Orientation
Name:	dwc_usbc31dptxphy_tsmc6ffns
Version:	4.03c
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare Cores Consumer 10G Type-C USB 3.1 DP PHY ATE Test Bench (Doc Version: 1.80a) ( PDF \| HTML ) SerDes PCB and Packaging Design Guide (Doc Version: 2.60a) ( PDF \| HTML ) Synopsys PHY IP High Speed SerDes Gate-Level Simulations (Doc Version: 1.12a) ( PDF \| HTML ) Databooks DesignWare Cores DP AUX-I2C PHY for TSMC6FF 1.8V (PHY Version: 4.03c) ( PDF \| HTML ) DesignWare Cores Type-C USB3.1 SSP+ / DP Alt PHY for TSMC6FF (PHY Version: 4.03c) ( PDF \| HTML ) Type-C USB3.1SSP+ / DP Alt PCS for the DesignWare Cores Type-C USB3.1SSP+ / DP Alt PHY (PCS Version: 3.54b ( PDF \| HTML ) Reference Manual DesignWare Cores Type-C USB3.1 SSP+ / DP Alt PHY for TSMC6FF Reference Manual (PHY Version: 4.03c) ( PDF \| HTML ) Release Notes DesignWare Cores Type-C USB3.1 DP PHY NS for TSMC6FF 1.8V Release Notes (PHY Version: 4.03c) ( TEXT )
Download:	dwc_usbc31dptxphy_tsmc6ffns
Product Code:	F409-0

Description:	USB-C 3.1/DP TX PHY for TSMC 7FF, North/South Poly Orientation
Name:	dwc_usbc31dptxphy_tsmc7ffns
Version:	4.03b
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
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Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare Cores Type-C USB 3.1 DP PHY ATE Test Bench (Doc Version: 1.71a) ( PDF \| HTML ) SerDes PCB and Packaging Design Guide (Doc Version: 2.60a) ( PDF \| HTML ) Synopsys PHY IP Compilation Using the LC and FC End-User Platform (Doc Version: 1.11a) ( HTML ) Synopsys PHY IP Consumer 10G Compilation Using the LC and FC End-User Platform (Doc Version: 1.11a) ( PDF ) Synopsys PHY IP High Speed SerDes Gate-Level Simulations (Doc Version: 1.12a) ( PDF \| HTML ) Databooks DesignWare Cores DP AUX-I2C PHY for TSMC7FF 1.8 V (PHY Version: 4.03b) ( PDF \| HTML ) DesignWare Cores Type-C USB3.1 SSP+ / DP Alt PHY for TSMC7FF (PHY Version: 4.03b) ( PDF \| HTML ) Type-C USB3.1SSP+ / DP Alt PCS for the DesignWare Cores Type-C - USB3.1SSP+ / DP Alt PHY (PCS Version: 3.52e) ( PDF \| HTML ) Release Notes DesignWare Cores Type-C USB3.1 SSP+ / DP Alt PHY for TSMC7FF Release Notes (PHY Version: 4.03b) ( TEXT ) White Papers USB 3.2: A USB Type-C Challenge for SoC Designers ( PDF ) USB 3.2: The Latest USB Type-C Challenge for SoC Designers ( PDF )
Download:	dwc_usbc31dptxphy_tsmc7ffns
Product Code:	C391-0