- Silicon Design & Verification
- Products
- Solutions
- Resources
- Services
- Community
- Training
- Silicon IP
- Products
- Markets
- Newsletter
- Customer Success
- News
- Resources
- Company
- About Us
- Investor Relations
- Community
- Newsroom
- Resources
- Careers
< Silicon Design & Verification
Silicon Design & Verification
< Products
< Products
< Products
< Products
< Products
< Products
< Products
Photonic Solutions
PIC Design Suite
< Silicon Design & Verification
< Solutions
< Solutions
< Solutions
Cloud
Synopsys on the Cloud
< Solutions
< Silicon Design & Verification
< Resources
< Resources
Verification
Articles
Blogs
Datasheets
Events
News
Newsletters
Success Stories
Videos
Webinars
White Papers
< Resources
< Silicon Design & Verification
< Services
< Services
< Services
< Silicon Design & Verification
< Community
Community
Community Overview
< Community
< Community
< Community
< Community
< Silicon Design & Verification
< Training
< Silicon Design & Verification
Training
Training and Education
< main menu
< Silicon IP
Silicon IP
< Products
< Products
Processor Solutions
ARC Processor IP
Embedded Vision Processor IP
Development Tools
Operating Systems
Ecosystem
ASIP Tools
< Products
Memories & Libraries
Logic Libraries
Memory Compliers
Duet Packages
HPC Design Kit
Embedded Test & Repair
Non-Volatile Memory
< Products
< Products
Analog IP
Data Converters
< Products
< Products
< Products
< Silicon IP
< Markets
< Silicon IP
Newsletter
< Silicon IP
Customer Success
< Silicon IP
News
< Resources
< Resources
< main menu
< Software Integrity
Polaris Platform
Comprehensive application security from developer to deployment
< Software Integrity
< Software Integrity
< Software Integrity
Professional Services
Strategy and programs that address security before, during and after development
< Software Integrity
< Tools
< Tools
< Tools
< Tools
< Software Integrity
< Services
Managed Security Testing
Managed SAST
Dynamic Analysis (DAST)
Penetration Testing
Mobile Application Security Testing
Network Security Testing
< Services
Professional Services
Strategy and Planning (BSIMM)
Architecture & Design
DevSecOps Integration
Cloud Security
Industry Solutions
< Services
< Software Integrity
< Training
< Training
Product Education
< Training
Community
< Software Integrity
< Solutions
< Solutions
< Resources
< Resources
< Software Integrity
< Software Integrity
Customers
< Partners
< Partners
Become a partner
< Software Integrity
< Software Integrity
Blog
< main menu
< About Us
Company
< About Us
< About Us
About Us
About Us
< Investor Relations
< About Us
Investor Relations
Investor Relations
< Community
< About Us
Community
Community
< Newsroom
< About Us
Newsroom
Newsroom
< Resources
< About Us
Resources
Resources
< Careers
< About Us
Careers
Careers
< main menu
Synopsys DesignWare SATA PHY IP
The DesignWare Mixed-Signal PHY IP for SATA and eSATA is designed for use in SoC solutions. The PHY integrates seamlessly with the DesignWare SATA AHCI Host digital controller to reduce design time and achieve first-pass silicon success. The SATA PHY provides a cost effective solution that is designed to meet the needs of today’s SATA designs. While extremely low in power consumption and area, the DesignWare SATA PHY substantially exceeds the electrical specifications in such key performance areas as jitter and receive sensitivity. The unique, advanced built-in diagnostics and sample automatic test equipment (ATE) test vectors available in the DesignWare PHY enable designers to implement complete at-speed production testing without expensive test equipment. Furthermore, the test vectors provide on-chip visibility into the actual link performance to quickly identify signal integrity issues.
The PHY includes a wide range of test capabilities including built-in per-channel BERTs, flexible fixed and random pattern generation, error counting on patterns or disparity, digital phase or voltage margining (bathtub curves), and built-in per channel scopes. The high-margin, robust SATA PHY architecture tolerates for manufacturing variations such as process, voltage and temperature. The SATA PHY passed interoperability testing utilizing industry-leading 65-nm, 40-nm, and 28-nm process technologies. You can view all Synopsys SATA videos here.
DesignWare SATA Complete Solution Datasheet DesignWare SATA PHY for Common Platform Processes Datasheet
|
| Synopsys Demonstrates DesignWare® SATA IP Interoperability See how Synopsys demonstrates proven interoperability with the complete DesignWare® SATA IP solution, consisting of digital controllers, mixed-signal PHY and Verification IP. This video consists of hardware demonstrations for the DesignWare SATA AHCI Host, Device, PHY and 6 Gb/s IP solutions. |
Highlights
Products
Downloads and Documentation
- Compliant with SATA/eSATA specification revision 3.3
- Excellent performance margin and receive sensitivity
- Very low power design; up to half the power compared to conventional PHYs
- Sample ATE test vectors provided for complete at-speed production testing
- Includes on-chip scope and built-in diagnostics for fast system verification
- Small, cost-effective die size
- Support for hot pluggable devices
- Optional spread-spectrum clock generation and absorption (SSC) with down-spread programmable from -5000ppm to -3000ppm
- Support for power down modes: partial, slumber and power down
- Silicon-proven in 65-nm, 40-nm, 28-nm and 16-nm process technologies
| SATA 6G PHY, GF 40LP, x1 | STARs | Subscribe |
| SATA 6G PHY, TSMC 40LP, X1 | STARs | Subscribe |
| SATA 6G PHY, TSMC 40LP, x2 | STARs | Subscribe |
| SATA 6G PHY, TSMC 65LP, x1 | STARs | Subscribe |
| SATA 6G PHY, GF 28SLP x1, East/West (horizontal) poly orientation | STARs | Subscribe |
| SATA 6G PHY, GF 28SLP x2, East/West (horizontal) poly orientation | STARs | Subscribe |
| SATA 6G PHY, SMIC 28HKMG x1, North/South (vertical) poly orientation | STARs | Subscribe |
| SATA 6G PHY, SMIC 40LL, x1 | STARs | Subscribe |
| SATA 6G PHY, SMIC 40LL, x2 | STARs | Subscribe |
| SATA 6G PHY, TSMC 16FFC x1, North/South (vertical) poly orientation | STARs | Subscribe |
| SATA 6G PHY, TSMC 16FF+GL x1, North/South (vertical) poly orientation | STARs | Subscribe |
| SATA 6G PHY, TSMC 16FF+GL x2, North/South (vertical) poly orientation | STARs | Subscribe |
| SATA 6G PHY, TSMC 16FF+LL x1, North/South (vertical) poly orientation | STARs | Subscribe |
| SATA 6G PHY, TSMC 16FF+LL x2, North/South (vertical) poly orientation | STARs | Subscribe |
| SATA 6G PHY, TSMC 28HPC+ x1, North/South (vertical) poly orientation | STARs | Subscribe |
| SATA 6G PHY, TSMC 28HPC+ x2, North/South (vertical) poly orientation | STARs | Subscribe |
| SATA 6G PHY, TSMC 28HPC18 x1, North/South (vertical) poly orientation | STARs | Subscribe |
| SATA 6G PHY, UMC 28HPC+ x1, North/South (vertical) poly orientation | STARs | Subscribe |
| SATA 6G PHY, UMC 28HPC x1, North/South (vertical) poly orientation | STARs | Subscribe |
| SATA 6G PHY, UMC 40LP, x1 | STARs | Subscribe |
| SATA 6G AR PHY, TSMC 28HPC18 x2, North/South (vertical) poly orientation | STARs | Subscribe |
