Virtual Prototyping
Accelerate pre-RTL embedded software development, hardware/software integration, and system validation
Architecture Design
Quickly explore tradeoffs in your SoC architecture to achieve optimal product performance and cost to avoid over- or under-design
FPGA-Based Prototyping
Accelerate the creation of your ASIC prototype with a high-speed hardware prototyping environment including a comprehensive software flow
Core Optimization
Differentiate your product with the right combination of performance, power and area for your most design-critical cores
Design Flow Deployment
Optimize your design flow to address the latest design challenges
Physical Design Assistance
Leverage our tape-out proven flows and project experience to implement your very-deep submicron chip
IP Integration & SoC Verification
Get to market faster and reduce SoC design and verification cost by applying best practices in RTL creation and functional verification
Synopsys DesignWare® IP for Serial ATA (SATA) Host with the Advanced Host Controller Interface (AHCI) supports 1.5, 3 and 6Gb/sec transfer speeds as defined by the SATA Specification Revision 3.0 (backwards compatible to SATA 2.6) and the AHCI 1.3 specification. To ease system level integration, the DesignWare SATA Host IP solution has an AMBA interface which extends the AHCI benefits to embedded system-on-chip (SoC) designs. The DesignWare SATA AHCI core IP has been fully verified with the industry-standard AHCI software drivers provided as part of the Linux® and Windows Vista™ operating systems. The DesignWare SATA AHCI IP solution has passed the SATA-IO Building Block Interoperability Testing, the golden standard of compliance to the SATA Specification.
The AHCI standard programming interface reduces custom platform software driver creation reducing the overall time from prototype to production. The DesignWare SATA digital host controller supports Asynchronous Notifications, Native Command Queuing (NCQ), Streaming NCQ and enables optimization for performance applications with up to 8 ports at a time. With its integrated DMA, high-speed operation is achieved without system overhead. Reduced gate count and very low power consumption is achieved by utilizing the set of highly configurable options which enable the core to be optimized based on the exact design requirements. The test environment for the digital host controller IP includes the DesignWare Verification IP, which enables SATA transactions generation, SATA protocol monitoring and AMBA subsystem transaction generation. Verilog-based tests are provided as examples to accelerate system integration.
You can view all Synopsys SATA videos here.DesignWare SATA Complete Solution Datasheet
SATA Host IP Demo Using a Port Multiplier and FIS-Based Switching See how DesignWare SATA host controller IP issues read/write commands to Port Multiplier-attached drives, while FIS-based switching interleaves the data packets to enhance the utilization of the 6 Gbps SATA link bandwidth.
