C Code Parallelization and Platform Generation for Heterogeneous Multicore Systems-on-Chips

SoC complexities are growing as more distinct system functions are combined in a single chip, requiring multicore architectures. Additionally, each system function (e.g. wireless modem, video coding, graphics) is becoming more complex, which may necessitate the introduction of multiple ASIPs for even a single system function. These evolutions bring new design challenges to system architects.

Notwithstanding the introduction of multicore subsystems, huge amounts of sequential, single-threaded application code are available and continue to be developed in the C language. Manually transforming such C code into parallel multithreaded software for a multicore subsystem is error-prone and requires costly and time-consuming verification. Furthermore, the multicore subsystem’s performance will depend on the capabilities of the communication fabric between the different processor cores.

MP Designer is a tool suite that addresses these multicore subsystem design challenges. MP Designer supports C code parallelization for multicore subsystems, aiming at an efficient load-balancing and a low communication cost between the processor cores, while ensuring correct communication and synchronization between tasks running on different cores. MP Designer can also generate an efficient communication fabric.

Heterogeneous Multicore Systems-on-Chip

Features

MP Designer's patented technology supports the following features:

Homogeneous SoC architectures with shared memory, as well as heterogeneous architectures with point-to-point communication links using distributed memory.
User-guided parallelization of sequential C source code, for implementation on multiprocessor SoC architectures. The user identifies different tasks in the C source program, and assigns them to individual processor cores by means of source-code pragmas that do not essentially change the source code.
Automatic global data-flow analysis of the code, to verify the feasibility of the parallelization proposed by the user.
Automatic insertion of all required software code for communication and synchronization between tasks assigned to processors. This is based on a communication library using FIFO queues, which can be automatically refined in platform-specific software code.
The parallelization kernel operates as a C source-to-source transformation tool. The original C source code structure is preserved as much as possible in the generated parallel code, facilitating visual analysis of the generated code by the user and efficient source-level debugging of the code in available software development kits (SDKs) for the different processors.
Graphical feedback about parallelization choices, in the form of task graphs, enabling users to quickly evaluate alternative partitions of their C code such that an efficient load balancing between the different processor cores is achieved.
MP Designer comes with a graphical multicore debugger,offering software designers complete visibility and control of all processor cores in their multicore architecture. The multicore debugger can connect to cycle- and instruction accurate instruction-set simulators of the cores, as well as to FPGA and ASIC implementations of the multicore system through a JTAG-based communication API, thus enabling multicore on-chip debugging.
MP Designer is currently intended for multicore architectures composed of ASIPs designed with the ASIP Designer tool suite. MP Designer easily interfaces with ASIP Designer-generated SDKs for each of the ASIPs, in order to compile and co-simulate the generated software code.
Optional platform generation capability, to automatically generate a SystemC based simulation model and a register-transfer level hardware model of a communication fabric between the different processor cores.

ASIP Designer - Application-Specific Processor Design Made Easy Brochure
ASIP Designer: Design Tool for Application-Specific Instruction-Set Processors Datasheet