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DesignWare USB 3.0 Device Controller IP
Synopsys' DesignWare® USB 3.0 Device Controller is a set of synthesizable soft IP that ASIC/FPGA designers can use to implement a complete USB 3.0 Device for 5 Gbps speeds. Integrating this digital, synthesizable logic into an ASIC, FPGA, or ASSP peripheral design helps to ensure complete USB 3.0 compliance, device functionality, and backward compatibility with USB 2.0. Optimizing development time and minimizing engineering risk, the DesignWare USB 3.0 Device Controller helps designers bring their host and peripheral designs to market faster for wired and wireless applications such as smart phones, tablets, TVs, set-top boxes, cameras, modems, game consoles, PCs, and telecommunications equipment.
The USB 3.0 Device Controller features industry-standard interfaces PIPE and UTMI/UTMI+ that connect to a USB 3.0 PHY. The SSIC features allows for the controller to interface with a MIPI M-PHY for low-power mobile applications.
DesignWare USB Controllers have shipped in over one billion units for electronics leading companies worldwide. Using DesignWare USB IP significantly reduces development time and engineering risk, bringing USB-based SoCs to market faster.
DesignWare USB IP is the most certified IP solution in the industry. With over 3,000 design wins, Synopsys' complete USB IP solution--consisting of controllers, PHYs, verification IP, drivers, and IP prototypes--enables designers to lower integration risk and speed time-to-market.
DesignWare SuperSpeed USB 3.0 Complete Solution
Highlights
Products
Downloads and Documentation
- Certified by the USB-IF
- SuperSpeed (5 Gbps) or High-Speed (480 Mbps) operation supported
- Optimized power management with SuperSpeed USB power savings modes, Uniform Power Format (UPF) and dual power rails
- Configurable data buffering options to fine-tune performance/area trade-offs
- Supports up to 16 bi-directional endpoints
- AXI and AHB interfaces or Native interface for bridging to other system buses
- Compatible with Synopsys' Certified USB 2.0 PHYs and USB 3.0 PHYs
- Verilog source code
- Verilog Test Bench included
| Description: | SuperSpeed USB 3.0 Device Controller Supporting SSIC and HSIC |
| Name: | dwc_usb_3_0_device |
| Version: | 3.30b |
| STARs: | Open and/or Closed STARs |
| myDesignWare: | Subscribe for Notifications |
| Product Type: | DesignWare Cores |
| Documentation: |
Hide Documents... Application Notes DesignWare Cores USB 3.0 PHY-Controller Integration Guide ( HTML | PDF ) Designware Cores SuperSpeed USB 3.0 Controller Synthesis and CTS Application Note ( PDF ) Setting Global Bus Configuration Registers ( HTML | PDF ) Complete Solution Datasheet DesignWare SuperSpeed USB 3.0 Complete Solution ( PDF ) Databooks Designware Cores SuperSpeed USB 3.0 Controller Databook (3.30b) ( PDF | HTML ) Designware Cores SuperSpeed USB 3.0 Controller Databook - with Change Bars (3.30b) ( PDF ) Datasheets DesignWare IP Prototyping Kits for USB 3.0 Host and Device ( PDF ) DesignWare IP Prototyping Kits for USB 3.1 Host and Device ( PDF ) DesignWare SuperSpeed USB 3.1 IP Solution ( PDF ) Doc Overview Designware Cores SuperSpeed USB 3.0 Controller Documentation Overview (3.30b) ( PDF ) Installation Guide DesignWare Cores SuperSpeed USB 3.0 Controller Installation Guide (3.30b) ( PDF ) Programming Guides Designware Cores SuperSpeed USB 3.0 Controller Programming Guide (3.30b) ( HTML | PDF ) Designware Cores SuperSpeed USB 3.0 Controller Programming Guide - with Change … ( PDF ) Release Notes Designware Cores SuperSpeed USB 3.0 Controller Release Notes (3.30b) ( PDF ) Success Stories DisplayLink Achieves First-Pass Silicon Success with DesignWare USB 3.0 IP ( PDF ) First-Pass Silicon Success for Myriad 2 Vision Processing Unit with DesignWare USB 3.0, … ( PDF ) Fujitsu Semiconductor Selects DesignWare DigRFv4 M-PHY and DigRF 3G PHY IP for … ( PDF ) Realtek Achieves First Silicon Success for Industry's First Certified USB 3.0 Card Reader … ( PDF ) Training Videos Clock Constraints ( PDF ) Clock Diagrams ( PDF ) Clocks Overview ( PDF ) Clocks in Power Management ( PDF ) Configuration Parameters Impacting Clocks ( PDF ) Configuring Advanced Parameters in DWC_usb3 Device Mode ( PDF ) Configuring Basic Parameters in DWC_usb3 Device Mode ( PDF ) Configuring DWC_usb3 Controller as a Device - Introduction ( PDF ) Configuring DWC_usb3 Controller as a Device - Summary ( PDF ) Configuring DWC_usb3 Controller as a Device - v3.00a (58.64) ( PDF ) Configuring DWC_usb3 for an Example Application ( PDF ) Configuring Device Parameters ( PDF ) Configuring PHY Parameters in DWC_usb3 Device Mode ( PDF ) Creating RTL for DWC_usb3 Device ( PDF ) DWC_usb3 Controller Clocks and Clock Synthesis - Introduction ( PDF ) DWC_usb3 Controller Clocks and Clock Synthesis - Summary ( PDF ) DWC_usb3 Controller Clocks and Clock Synthesis - v3.00a (34:54) ( PDF ) Example Timing Diagrams ( PDF ) Generated Clocks ( PDF ) Hibernation ( PDF ) Implementing Hibernation ( PDF ) Managing Power in DWC_usb3 - Introduction ( PDF ) Managing Power in DWC_usb3 - Overview ( PDF ) Managing Power in DWC_usb3 - Summary ( PDF ) Managing Power in DWC_usb3 - v2.80a (45:38) ( PDF ) User Guide Designware Cores SuperSpeed USB 3.0 Controller User Guide (3.30b) ( HTML | PDF ) White Papers Debugging SuperSpeed USB Software Using Virtual Prototypes ( PDF ) USB 3.2: A USB Type-C Challenge for SoC Designers ( PDF ) USB 3.2: The Latest USB Type-C Challenge for SoC Designers ( PDF ) |
| Toolsets: | Qualified Toolsets |
| Download: | USB3-Device-AHB |
| Product Code: | 6793-0 |
| Description: | SuperSpeed USB 3.0 Dual Role Device Controller, Configurable for SSIC and HSIC |
| Name: | dwc_usb_3_0_drd |
| Version: | 3.30b |
| STARs: | Open and/or Closed STARs |
| myDesignWare: | Subscribe for Notifications |
| Product Type: | DesignWare Cores |
| Documentation: |
Hide Documents... Application Notes DesignWare Cores USB 3.0 PHY-Controller Integration Guide ( HTML | PDF ) Designware Cores SuperSpeed USB 3.0 Controller Synthesis and CTS Application Note ( PDF ) Setting Global Bus Configuration Registers ( HTML | PDF ) Complete Solution Datasheet DesignWare SuperSpeed USB 3.0 Complete Solution ( PDF ) Databooks Designware Cores SuperSpeed USB 3.0 Controller Databook (3.30b) ( PDF | HTML ) Designware Cores SuperSpeed USB 3.0 Controller Databook - with Change Bars (3.30b) ( PDF ) Datasheets DesignWare IP Prototyping Kits for USB 3.0 Host and Device ( PDF ) DesignWare IP Prototyping Kits for USB 3.1 Host and Device ( PDF ) DesignWare SuperSpeed USB 3.1 IP Solution ( PDF ) Doc Overview Designware Cores SuperSpeed USB 3.0 Controller Documentation Overview (3.30b) ( PDF ) Installation Guide DesignWare Cores SuperSpeed USB 3.0 Controller Installation Guide (3.30b) ( PDF ) Programming Guides Designware Cores SuperSpeed USB 3.0 Controller Programming Guide (3.30b) ( HTML | PDF ) Designware Cores SuperSpeed USB 3.0 Controller Programming Guide - with Change … ( PDF ) Release Notes Designware Cores SuperSpeed USB 3.0 Controller Release Notes (3.30b) ( PDF ) Success Story First-Pass Silicon Success for Myriad 2 Vision Processing Unit with DesignWare USB 3.0, … ( PDF ) Training Videos Clock Constraints ( PDF ) Clock Diagrams ( PDF ) Clocks Overview ( PDF ) Clocks in Power Management ( PDF ) Configuration Parameters Impacting Clocks ( PDF ) DWC_usb3 Controller Clocks and Clock Synthesis - Introduction ( PDF ) DWC_usb3 Controller Clocks and Clock Synthesis - Summary ( PDF ) DWC_usb3 Controller Clocks and Clock Synthesis - v3.00a (34:54) ( PDF ) Example Timing Diagrams ( PDF ) Generated Clocks ( PDF ) Hibernation ( PDF ) Implementing Hibernation ( PDF ) Managing Power in DWC_usb3 - Introduction ( PDF ) Managing Power in DWC_usb3 - Overview ( PDF ) Managing Power in DWC_usb3 - Summary ( PDF ) Managing Power in DWC_usb3 - v2.80a (45:38) ( PDF ) User Guide Designware Cores SuperSpeed USB 3.0 Controller User Guide (3.30b) ( HTML | PDF ) White Papers USB 3.2: A USB Type-C Challenge for SoC Designers ( PDF ) USB 3.2: The Latest USB Type-C Challenge for SoC Designers ( PDF ) |
| Toolsets: | Qualified Toolsets |
| Download: | USB3-Device-AHB |
| Product Code: | 7567-0 |