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DesignWare USB 3.0 Device Controller IP
Synopsys' DesignWare® USB 3.0 Device Controller is a set of synthesizable soft IP that ASIC/FPGA designers can use to implement a complete USB 3.0 Device for 5 Gbps speeds. Integrating this digital, synthesizable logic into an ASIC, FPGA, or ASSP peripheral design helps to ensure complete USB 3.0 compliance, device functionality, and backward compatibility with USB 2.0. Optimizing development time and minimizing engineering risk, the DesignWare USB 3.0 Device Controller helps designers bring their host and peripheral designs to market faster for wired and wireless applications such as smart phones, tablets, TVs, set-top boxes, cameras, modems, game consoles, PCs, and telecommunications equipment.
The USB 3.0 Device Controller features industry-standard interfaces PIPE and UTMI/UTMI+ that connect to a USB 3.0 PHY. The SSIC features allows for the controller to interface with a MIPI M-PHY for low-power mobile applications.
DesignWare USB Controllers have shipped in over one billion units for electronics leading companies worldwide. Using DesignWare USB IP significantly reduces development time and engineering risk, bringing USB-based SoCs to market faster.
DesignWare USB IP is the most certified IP solution in the industry. With over 3,000 design wins, Synopsys' complete USB IP solution--consisting of controllers, PHYs, verification IP, drivers, and IP prototypes--enables designers to lower integration risk and speed time-to-market.
USB 3.0 University
If you are new to designing with USB, or looking for tips on implementing USB 3.0 IP, Synopsys' USB 3.0 University has a session for you. From a basic USB overview, to implementing USB on FPGAs, to top-level synthesis, you'll find the information you need in this instructional video series.
DesignWare SuperSpeed USB 3.0 Complete Solution
Highlights
Products
Downloads and Documentation
- Certified by the USB-IF
- SuperSpeed (5 Gbps) or High-Speed (480 Mbps) operation supported
- Optimized power management with SuperSpeed USB power savings modes, Uniform Power Format (UPF) and dual power rails
- Configurable data buffering options to fine-tune performance/area trade-offs
- Supports up to 16 bi-directional endpoints
- AXI and AHB interfaces or Native interface for bridging to other system buses
- Compatible with Synopsys' Certified USB 2.0 PHYs and USB 3.0 PHYs
- Verilog source code
- Verilog Test Bench included