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DesignWare PHY IP for PCI Express 1.1

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Synopsys' DesignWare® PHY IP for PCI Express® (PCIe®) 1.1, operating at 2.5 Gbps, is designed with high-speed mixed-signal custom CMOS circuitry for integration in root complex, endpoint, dual-mode, and switch applications. The PCIe PHY includes all of the required logical and physical design files needed for integration in a SoC design. Supporting the PCIe 1.1 and PHY Interface for PCIe (PIPE) specfications, the PHY includes all of the required logical and physical design files for use in SoC designs. Validated compatibility with the DesignWare Endpoint Controller IP for PCIe enable easy integration of the PHY into SoCs for a variety of applications - high-end computing, server, data center, consumer and graphics.

The low power, small area PHY substantially exceeds the electrical specifications in such key performance areas as jitter tolerance and receive sensitivity.

Synopsys offers a portfolio of silicon-proven IP for PCIe consisting of controllers, PHYs, verification IP, IP Prototyping Kits, Software Development Kits and Interface IP Subsystems. As the industry standard for PCIe, Synopsys' solution is in volume production and has been successfully implemented in a wide range of applications.

DesignWare IP for PCI Express 1.1 PHY Datasheet
DesignWare IP for PCI Express Complete Solution Datasheet
 

  • Supports a wide range of configurations including 1.0v & 1.2v core supplies and 2.5v & 3.3v I/O supplies
  • Supports a wide range of PCI Express bus widths (up to x16 support)
  • supports PCIe 1.0a and 1.0a Errata and PIPE interface to ensure interoperability and ease of integration with higher protocol levels
  • Supports all power-down states for highly efficient operation
  • Full support for beaconing, receiver detection and electrical idle
  • Reliable link operation across channel manufacturing operation (BER<10-18)
  • Unique, built-in diagnostics enables visibility into link performance
  • Automatic Test Equipment (ATE) test vectors for complete, at-speed production testing
  • Silicon proven for 130-nm, 90-nm, 65-nm, 40-nm and 28-nm processes
PCIe PHY, TSMC 40LP, x1STARsSubscribe

  Description PCIe PHY, TSMC 40LP, x1
  Name dwc_pcie1phy-tsmc40lp-x1
  Version 3.4a
  STARs Open and/or Closed STARs
  myDesignWare Subscribe for Notifications
  Product Type DesignWare Cores
  Documentation
  Download PCIe-PHY_TSMC_40LP_x1
  Product Code 7405-0