Synopsys provides designers with silicon-proven, configurable DesignWare® eUSB2 PHYs that are compliant with the USB-Implementers Forum (USB-IF) eUSB2 and USB 2.0 specifications. Synopsys' DesignWare eUSB2 PHY IP has industry's best combination of low area and low power in leading process technologies from 7nm and below.
The DesignWare eUSB2 IP is built on years of customer successes with Synopsys’ silicon-proven USB PHY product line, which has been ported to over 100 process nodes ranging from 180nm to 5nm.
With over 3,000 design wins and over 4 billion silicon-proven units shipped, Synopsys' USB IP solution, consisting of digital controllers, PHYs, IP subsystems, and verification IP, enables designers to lower integration risk and speed time-to-market.
DesignWare eUSB2 IP Solution Datasheet
Enabling USB 2.0 in Advanced Process Nodes Using DesignWare eUSB2 IPUSB 2.0 has been around for over 20 years and is the world's most popular wired interconnect standard. Join Morten Christiansen and Gervais Fong as they discuss how the new eUSB2 standard enables USB 2.0 connectivity for SoCs in the most advanced process nodes.
Downloads and Documentation
- Designed for 7nm processes and below
- Supports the USB 2.0 protocol and High Speed, Full Speed, and Low Speed data rates
- eUSB2 PHYs supports USB 2.0, 3.0, 3.1 and 3.2 Device, Host and Dual Role configurations
|eUSB 2.0 PHY - TSMC N5 x1, North/South (vertical) poly orientation||STARs