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Synopsys XGMAC DesignWare® IP is compliant with the IEEE 802.3 specification for 1G/10G Ethernet. It interfaces to the PHY layer through the XGMII interface, and to the system through a FIFO or AMBA AXI interface. To ease SoC integration, the IP is highly configurable so it can tailor its feature set to target applications supporting speeds of 1G, 2.5G or 10G. The XGMAC can be integrated with the DesignWare Ethernet PCS and the DesignWare XAUI PHY IP for a complete 10 Gigabit Ethernet solution. DesignWare 10 Gigabit Ethernet IP Complete Solution Datasheet
DesignWare XGMAC 10G Ethernet MAC Datasheet
General Features
- Supports IEEE 802.3az-2010 Energy Efficient Ethernet
- Supports IEEE 1588-2008 Precision Clock Synchronization Protocol for Networked Measurement and Control Systems
- Supports VLAN tag processing in compliance with IEEE 802.1Q-2005 standard
- Fully compliant IEEE 802.3-2008 Clause 46 XGMII interface to communicate with an external XGMII PHY
- External 1G PHY support with a GMII interface compliant with Clause 35 of the IEEE 802.3-2008 standard
- Supports IEEE 802.3 flow control and priority based flow control (PFC)
- IPv4/6 Header Checksum processing for Transmit and Receive
- TCP/UDP/ICMP Checksum insertion and processing for Transmit and Receive
- Complete Network statistics (optional) with RMON/MIB counters (RFC2819/RFC2665)
- Optional MDIO Master interface for PH&Y management and device configuration
- Advanced power management features
- Configurable for 1G, 2.5G or 10G speeds
PHY Interface Features
- Support for XGMII interface at double clock rate or data width
- Support for GMII interface for 1G configurations
- Transmit pace rate (programmable), i.e., IPG adjustment to match MAC to PHY rates to SONET /SDH rates
- Local link fault detection and remote fault transmission and detection
System Interface Features
- Native FIFO interface for low-latency applications
- Optional AMBA AXI Master system interface with AXI slave or APB port for CSR access
- Supports 64-bit or 128-bit data interface
- Configurable Big Endian and Little Endian support
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