DesignWare Ethernet XGMAC IP

General Features

• Compliant IEEE 802.3az-2010 Energy Efficient Ethernet
• Compliant IEEE 1588-2008 Precision Time Protocol (PTP) for networked measurement and control systems
• Compliant with the consortium specifications
• Supports VLAN tag processing in compliance with IEEE 802.1Q-2005 standard
• Fully compliant IEEE 802.3-2008 Clause 46 XGMII interface to communicate with an external XGMII PHY
• External 1G PHY support with a GMII interface compliant with Clause 35 of the IEEE 802.3-2008 standard
• Supports IEEE 802.3 flow control and priority-based flow control (PFC)
• IPv4/6 Header Checksum processing for Transmit and Receive
• TCP/UDP/ICMP Checksum insertion and processing for Transmit and Receive
• Complete Network statistics (optional) with RMON/MIB counters (RFC2819/RFC2665)
• MDIO Master interface for PHY management and device configuration
• Advanced power management features
• Supports 1G, 2.5G, 5G or 10G speeds

PHY Interface Features

• Support for XGMII interface at double clock rate or data width
• Support for GMII interface for 1G configurations
• Supports transmit pace rate adjustment (through IDLE character addition) to match MAC to PHY SONET/SDH rates in 10G operation
• Local link fault detection and remote fault transmission and detection

System Interface Features

• Native FIFO interface for low-latency applications
• Optional AMBA AXI Master system interface with AXI slave or APB port for CSR access
• Supports 64-bit or 128-bit data interface
• Configurable Big Endian and Little Endian support