The DesignWare Ethernet Physical Coding Sublayer (PCS) IP is compliant with the IEEE 802 and consortium specifications for 1G, 2.5G, 5G and 10G Ethernet PCS layers. The DesignWare Ethernet PCS core provides an interface between the Media Access Control (MAC) and Physical Medium Attachment Sublayer (PMA) through a Media independent interface. With support for GMII for 1000BASE-X PCS defined for a single lane which operates at 125 MHz to support 1000BASE-X PMA and XGMII for 10GBASE-X PCS defined for four lanes which operate at 312.5 MHz on each lane to support 10GBASE-X and 10GBASE-R PMA. To maintain transition density and DC balancing, the 1000BASE-X and 10GBASE-X PCS use 8B/10B encoding/decoding and 10GBASE-R PCS uses 64B/66B encoding or decoding and the scrambling technique.
The DWC_xpcs core is designed to support the following derivatives of the PCS layer:
- 1000BASE-X or SGMII
- 10GBASE-KX4, 10GBASE-KR, 1000BASE-KX
The DesignWare Ethernet PCS IP is verified using state-of-the-art methodologies including the RTL design, verification, hardware verification and interoperability tests. The IP is easily configured with a user-friendly application interface for easy functional and implementation objectives to meet design requirements, making the DesignWare Ethernet PCS IP a streamlined and flexible solution. Coupled with the DesignWare XGMAC IP and a configurable Media Access Control (MAC) that supports 1G/2.5G/5G/10G Ethernet applications, the Ethernet PCS IP offers easy SoC integration into 1G/2.5G/5G/10G Ethernet designs.
The DesignWare Ethernet IP solutions consist of configurable controllers and silicon-proven PHYs supporting speeds of up to 100G, verification IP, IP Prototyping Kits, Software Development Kits and Interface IP Subsystems. DesignWare Ethernet PCS Datasheet
DesignWare XAUI PHY Datasheet
- Compliant with IEEE 802.3ae Clause 47 and Clause 48 for XGXS applications and IEEE 802.3ap Clause 36, Clause 45, Clause 48 and Clause 73 for 1000B-KX, 10GBASE-KX4, auto negotiation and consortium specifications
- Supports Clause 37 auto negotiation for 1000BASE-X applications
- Compliant with Clause 36 and Clause 37 auto negotiation for 1000BASE-X applications
- Easily configurable for 10 Gigabit Ethernet applications using XGXS-PCS or 10GBASE-X PCS and/or Gigabit application like 1000BASE-X
- Option to support Industry standards like RXAUI and SGMII (10/100/1000 Mbps operating modes)
- Backplane Ethernet for KX and KX4, KX only or KX4 only with KX configurations capable of 2.5 Gigabit Ethernet speeds simply by increasing the clock frequency
- Conversion of dual data rate XGMII to single data rate 312.5 MHz data-bus
- Optional conversion of double data width (64 bit) XGMII operation with 156.25 MHz clock to single data rate (32-bit) operating with 312.5 MHz clock
- Seamlessly integrates with the DesignWare XAUI-PHY SerDes
- Option to have either IEEE 802.3 Clause 45 compliant MDIO serial interface or parallel micro-controller interface for the host.
- Conversion of XGMII idle control characters to a randomized sequence of code groups to enable lane synchronization, land to lane alignment and clock rate compensation
- 8B/10B encoding to convert the binary data to 10-bit encoded data for each lane
- Lane synchronization on receive side to determine code-group boundaries
- De-skew of all received code groups to an alignment pattern with a maximum allowed skew over 5 cycles
- Clock rate compensation in which idle characters are inserted or deleted to compensate for the frequency variations between the recovered clock and the local clock with a maximum allowed variation between the clocks of 200ppm
- Supports internal loop-back on the XGMII for debugging through receive to transmit digital path and loopback control of the SerDes PHY transmit to SerDes PHY receive lane
- Link status reporting for faulty conditions and multiple options for error status and statistics available for monitoring and debugging