The Synopsys Universal DDR Protocol Controller (uPCTL) serves the memory control needs of applications with simple transactions that do not require an internal scheduler. The streamlined command based low-latency native interface (NIF) also enables the uPCTL to be integrated with a custom application specific scheduler.
The uPCTL is a bridge between a system-on-chip (SoC) application bus and a PHY for a DDR SDRAM, such as the Synopsys DDR PHYs. The uPCTL and the DDR PHY together handle the details of the DDR protocol, allowing the application to access memory via simple on-chip bus read/write requests.
The uPCTL connects to DDR PHYs via a DFI 2.1 interface to create a complete memory interface and control solution. The controller includes software configuration registers, which are accessed through an AMBA 2.0 APB interface.
Synopsys Universal DDR Memory and Protocol Controllers Datasheet