DesignWare ARC 710D Processor Core

The DesignWare® ARC™ 710D configurable processor core is designed for embedded processing functions within system-on-chips (SoCs). The ARC 710D processor core is optimized for hard, real-time processing, where high speed and deterministic response are required. Small size, low power and configurable architectural features make the DesignWare ARC 710D processor core ideal for multi-core and other applications.

Powerful DSP options enable the DesignWare ARC 710D processor core to perform more of the functions on the SoC, eliminating the need for separate logic or DSP blocks. Optionally, custom instruction extensions may be incorporated to achieve application performance levels unattainable with fixed architecture cores.

The DesignWare ARC 710D processor core is supported by a full suite of software and hardware development tools. The suite includes the MetaWare Development Kit, which generates highly efficient code that is ideal for embedded applications and ARC simulators including xCAM and nSIM, and the ARChitect configuration tool.

DesignWare ARC 710 Datasheet

Highlights

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A highly configurable architecture allows SoC designers to include only the core features that are required for their specific application, resulting in smaller die size and lower power than can be achieved with a fixed core.
User-defined instruction and register extensions deliver 5 - 100 times performance improvement of critical routines.
Cacheless design and closely coupled (single-cycle) memories provide fast, predictable computation.
Built-in DSP features include instruction and register extensions that accelerate signal processing algorithms.
Optional DesignWare ARC XY Advanced DSP subsystem delivers the performance of dedicated DSP cores.
DesignWare ARCompact™ 16- / 32-bit Instruction Set Architecture reduces code size by up to 40 percent compared to 32-bit only instruction sets.
Inter-processor communication ISA support, multi-processor debug environment and flexible interfaces enable multi-core designs.
JTAG debug port and optional embedded hardware breakpoints facilitate software debug.
Delivered as synthesizable RTL source code (Verilog®), the DesignWare ARC 710D core is fully compatible with industry standard design methodologies and tool flows.

ARC 710D high-performance, 32-bit processor core with optional ARC XY, DSP, FPU

STARs

Description:	ARC 710D high-performance, 32-bit processor core with optional ARC XY, DSP, FPU
Name:	dwc_arc_710d_core
Version:	4.12a
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes ARC Processors Not Susceptible to Meltdown and Spectre Vulnerabilities ( PDF ) Design-For-Test Implementation ( PDF ) Getting Started with Embedded Programming on ARC ( PDF ) Optimizing DPFPfast Floating Point Extension for Lower Cycle Count ( PDF ) Pipeline Stall Hazards ( PDF ) XY-Memory Pointer Buffer Update ( PDF ) Databooks ARC 700 Databook ( PDF ) ARC FPGA Peripherals Databook ( PDF ) ARC RDF Synplicity Databook ( PDF ) ARC RDF Xilinx Databook ( PDF ) Datasheet DesignWare ARC 710 Datasheet ( PDF ) QuickStarts ARC Synopsys RDF Getting Started ( PDF ) ML50x Development Board Getting Started 4.90b ( PDF ) Reference Manuals ARC 700 DSPlib Reference ( PDF ) ARC HAPS51 Board Connections and Settings Reference Manual ( PDF ) ARCompact ISA Programmers Reference ( PDF ) ARC 700 DSP Options Reference ( PDF ) Release Notes ARC ML509 Development Systems Release Notes ( PDF ) ARC Synopsys RDF Release Notes ( PDF ) Success Story ARC 700 on Altera FPGA ( PDF ) Tutorial EIA Cookbook ( PDF ) User Guide ARC Synopsys RDF User Guide ( PDF )
Download:	arc_ARC700_Series_bundle
Product Code:	4794-0, 8026-0, 8027-0, 8028-0