dwc_comp_ts07n0g41p11sadul02ms
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IP Directory Component Detail
| Description: |
Single Port, Ultra High Density SRAM 2M Sync Compiler, TSMC 7FF Periphery Optional-Vt/Cell Std Vt |
| Name: |
dwc_comp_ts07n0g41p11sadul02ms |
| Version: |
a19 |
| ECCN: |
3E991/NLR |
| STARs: |
Open and/or Closed STARs |
| myDesignWare: |
Subscribe for Notifications |
| Product Type: |
DesignWare Embedded Memory IP |
| Documentation: |
Hide Documents...
Application Notes Datasheet Read/Write Power Correlation with Liberty and PTPX ( PDF )
FRAM plugin usage ( PDF )
TSMC 16nm and Smaller Geometries Memory Compilers IP UPF Support ( PDF )
TSMC N7 Memory Compilers Compiler Modes ( PDF )
TSMC N7 Memory Compilers SOC Integration Guidelines ( PDF )
TSMC N7 and Smaller Geometries Memory Compilers CMM Plugin ( PDF )
TSMC N7 and Smaller Geometries Memory Compilers TEST_RNM, TESTRWM and TEST1 Modes ( PDF )
TSMC N7/N6 Memory Compilers Address and IO Scrambling Information ( PDF )
TSMC N7/N6 Memory Compilers Power Modes ( PDF )
TSMC N7/N6 Memory Compilers Read Margin and Assist Settings ( PDF )
TSMC N7/N6 Memory Compilers Redundancy and BIST Features ( PDF )
TSMC N7/N6 Memory Compilers SOC Integration Guidelines ( PDF )
TSMC N7/N6 NDM Plugin User Guide ( PDF )
Verilog User Guide ( PDF )
QuickStart Embed-It! Integrator Quick Start Guide ( PDF )
Release Notes DesignWare Single Port Ultra High Density Leakage Control SRAM 2M Sync Compiler For TSMC 7nm FinFET P-Optional Vt/Cell Std Vt Process - Release Notes ( TEXT )
User Guide DesignWare Single Port Ultra High Density Leakage Control SRAM 2M Sync Compiler For TSMC 7nm FinFET P-Optional Vt/Cell Std Vt Process - User Guide ( PDF )
|
| Download: |
v-comp_ts07n0g41p11sadul02ms |
| Product Code: |
C153-0 |
