Assessing ESD Sensitivity of Interface IP Using Charged Device Model

Assessing ESD Sensitivity of Interface IP Using Charged Device Model

An electronic device is susceptible to Electrostatic Discharge (ESD) damage during its entire life cycle, especially from the completion of the silicon wafer processing to when the device is assembled in the system. The most commonly used ESD test models are the Human Body Model (HBM) and the Charged Device Model (CDM). Both models assess the ESD sensitivity of a device, however due to the rapid growth in automated handling, manufacturing and assembly of electronic devices, CDM has become the primary real world ESD event model. This white paper describes the CDM ESD event and explains how IC designers can obtain actual CDM voltage levels of an SoC using the peak current level measured during the interface IP CDM qualification phase.

The topics addressed in this white paper are:

• Principles of the Charged Device Model
• Testing in a CDM Simulation Environment
• On-Chip ESD Network
• Using Peak Current for Interface IP CDM Qualification
• Assessing the IP CDM Performance in the Final Product

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